+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014 Gateworks Corporation
* Author: Tim Harvey <tharvey@gateworks.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <env.h>
+#include <hang.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
-#include <environment.h>
+#include <env.h>
#include <i2c.h>
#include <spl.h>
#include "gsc.h"
#include "common.h"
-DECLARE_GLOBAL_DATA_PTR;
-
#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
.p0_mpwrdlctl = 0x33382C31,
};
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190017,
+ .p0_mpwldectrl1 = 0x00140026,
+ .p1_mpwldectrl0 = 0x0021001C,
+ .p1_mpwldectrl1 = 0x0011001D,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43380347,
+ .p0_mpdgctrl1 = 0x433C034D,
+ .p1_mpdgctrl0 = 0x032C0324,
+ .p1_mpdgctrl1 = 0x03310232,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3C313539,
+ .p1_mprddlctl = 0x37343141,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x36393C39,
+ .p1_mpwrdlctl = 0x42344438,
+};
+
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x003C003C,
+ .p0_mpwldectrl1 = 0x001F002A,
+ .p1_mpwldectrl0 = 0x00330038,
+ .p1_mpwldectrl1 = 0x0022003F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42410244,
+ .p0_mpdgctrl1 = 0x4234023A,
+ .p1_mpdgctrl0 = 0x022D022D,
+ .p1_mpdgctrl1 = 0x021C0228,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x484A4C4B,
+ .p1_mprddlctl = 0x4B4D4E4B,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33342B32,
+ .p1_mpwrdlctl = 0x3933332B,
+};
+
static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x001B0016,
.p1_mpwrdlctl = 0x3F36363F,
};
+static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001F003F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x001F004E,
+ .p1_mpwldectrl1 = 0x0059001F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42220225,
+ .p0_mpdgctrl1 = 0x0213021F,
+ .p1_mpdgctrl0 = 0x022C0242,
+ .p1_mpdgctrl1 = 0x022C0244,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x474A4C4A,
+ .p1_mprddlctl = 0x48494C45,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x3F3F3F36,
+ .p1_mpwrdlctl = 0x3F36363F,
+};
+
static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x002A0025,
else
calib = &mx6sdl_256x16_mmdc_calib;
debug("4gB density\n");
+ } else if (width == 16 && size_mb == 1024) {
+ mem = &mt41k512m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_512x32_mmdc_calib;
+ debug("8gB density\n");
} else if (width == 32 && size_mb == 256) {
/* Same calib as width==16, size==128 */
mem = &mt41k64m16jt_125;
} else if (width == 64 && size_mb == 512) {
mem = &mt41k64m16jt_125;
debug("1gB density\n");
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_64x64_mmdc_calib;
+ else
+ calib = &mx6sdl_64x64_mmdc_calib;
} else if (width == 64 && size_mb == 1024) {
mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
calib = &mx6sdl_128x64_mmdc_calib;
debug("2gB density\n");
} else if (width == 64 && size_mb == 2048) {
- mem = &mt41k256m16ha_125;
- if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &mx6dq_256x64_mmdc_calib;
- else
- calib = &mx6sdl_256x64_mmdc_calib;
- debug("4gB density\n");
+ switch(board_model) {
+ case GW5905:
+ /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */
+ mem = &mt41k128m16jt_125;
+ debug("2gB density - 2 chipsel\n");
+ if (!is_cpu_type(MXC_CPU_MX6Q)) {
+ calib = &mx6sdl_128x64x2_mmdc_calib;
+ sysinfo.ncs = 2;
+ sysinfo.cs_density = 10; /* CS0_END=39 */
+ sysinfo.cs1_mirror = 1; /* mirror enabled */
+ }
+ break;
+ default:
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x64_mmdc_calib;
+ else
+ calib = &mx6sdl_256x64_mmdc_calib;
+ debug("4gB density\n");
+ break;
+ }
} else if (width == 64 && size_mb == 4096) {
switch(board_model) {
case GW5903:
/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
mem = &mt41k256m16ha_125;
- debug("4gB density\n");
+ debug("4gB density - 2 chipsel\n");
if (!is_cpu_type(MXC_CPU_MX6Q)) {
calib = &mx6sdl_256x64x2_mmdc_calib;
sysinfo.ncs = 2;
writel(0x000003FF, &ccm->CCGR6);
}
-static void gpr_init(void)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* enable AXI cache for VDOA/VPU/IPU */
- writel(0xF00000CF, &iomux->gpr[4]);
- /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
- writel(0x007F007F, &iomux->gpr[6]);
- writel(0x007F007F, &iomux->gpr[7]);
-}
-
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
/* setup AXI */
gpr_init();
- /* iomux and setup of i2c */
+ /* iomux and setup of uart/i2c */
setup_iomux_uart();
- setup_ventana_i2c();
+ setup_ventana_i2c(0);
+ setup_ventana_i2c(1);
/* setup GP timer */
timer_init();
spl_dram_init(8 << ventana_info.sdram_width,
16 << ventana_info.sdram_size,
board_model);
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
}
void board_boot_order(u32 *spl_boot_list)
projects / oweals / u-boot.git / blobdiff