#include <fm_eth.h>
#include "t4rdb.h"
+#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
+ u8 sw;
printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
+
+ sw = CPLD_READ(vbank);
+ sw = sw & CPLD_BANK_SEL_MASK;
+
+ if (sw <= 7)
+ printf("vBank: %d\n", sw);
+ else
+ printf("Unsupported Bank=%x\n", sw);
puts("SERDES Reference Clocks:\n");
printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
flush_dcache();
invalidate_icache();
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
return 0;
}
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
+
+ return 0;
}
/*