T1042RDB_PI_NAND_SECURE_BOOT: Guard t104xrdb SPL env code

[oweals/u-boot.git] / board / freescale / t104xrdb / tlb.c

diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 078947902fd952b1f2eee3cd25d3bc87deaa7553..9dcba7933ff99c0bbf8b336b111129e765b67306 100644 (file)
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -29,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 1 */
        /* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
-       !defined(CONFIG_SECURE_BOOT)
+       !defined(CONFIG_NXP_ESBC)
        /*
         * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
         * SRAM is at 0xfffc0000, it covered the 0xfffff000.
@@ -38,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_256K, 1),
 
-#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
        /*
         * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
         * the physical address of the SRAM is at 0xbffc0000,