Merge tag 'dm-pull-3dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

[oweals/u-boot.git] / board / freescale / t104xrdb / eth.c

diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 7581a4cdd44b95a685720a3c052064116742ba7b..107d28da33becd3630b6e2a88bef5fb06b80f6e2 100644 (file)
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -11,7 +10,7 @@
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <malloc.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <vsc9953.h>
 
 #include "../common/fman.h"
@@ -43,14 +42,16 @@ int board_eth_init(bd_t *bis)
                int idx = i - FM1_DTSEC1;
 
                switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
                case PHY_INTERFACE_MODE_SGMII:
-                       /* T1040RDB only supports SGMII on DTSEC3 */
+                       /* T1040RDB & T1040D4RDB only supports SGMII on
+                        * DTSEC3
+                        */
                        fm_info_set_phy_address(FM1_DTSEC3,
                                                CONFIG_SYS_SGMII1_PHY_ADDR);
                        break;
 #endif
-#ifdef CONFIG_T1042RDB
+#ifdef CONFIG_TARGET_T1042RDB
                case PHY_INTERFACE_MODE_SGMII:
                        /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
                        if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
@@ -59,6 +60,20 @@ int board_eth_init(bd_t *bis)
                        fm_info_set_phy_address(FM1_DTSEC3,
                                                CONFIG_SYS_SGMII1_PHY_ADDR);
                        break;
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+               case PHY_INTERFACE_MODE_SGMII:
+                       /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+                        *  & DTSEC3
+                        */
+                       if (FM1_DTSEC1 == i)
+                               phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+                       if (FM1_DTSEC2 == i)
+                               phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+                       if (FM1_DTSEC3 == i)
+                               phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+                       fm_info_set_phy_address(i, phy_addr);
+                       break;
 #endif
                case PHY_INTERFACE_MODE_RGMII:
                        if (FM1_DTSEC4 == i)