+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- const char dimm_model[] = "RAW timing DDR";
-
- if ((controller_number == 0) && (dimm_number == 0)) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->half_strength_driver_enable = 1;
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x59;
+#else
popts->half_strength_driver_enable = 0;
+#endif
/*
* Write leveling override
*/
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
}
#if defined(CONFIG_DEEP_SLEEP)
}
#endif
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
-
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
#else
dram_size = fsl_ddr_sdram_size();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}