(and variants). Variants inclued T1042 presonality of T1040, in which
case T1040RDB can also be called T1042RDB.
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
(a personality of T1040 SoC). The board is similar to T1040RDB but is
designed specially with low power features targeted for Printing Image Market.
+The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
+The board is re-designed T1040RDB board with following changes :
+ - Support of DDR4 memory and some enhancements
+
+The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
+The board is re-designed T1040RDB board with following changes :
+ - Support of DDR4 memory
+ - Support for 0x86 serdes protocol which can support following interfaces
+ - 2 RGMII's on DTSEC4, DTSEC5
+ - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
+
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board Si Protocol Targeted Market
+-------------------------------------------------------------------------
+T1040RDB T1040 0x66 Networking
+T1040RDB T1042 0x86 Networking
+T1042RDB_PI T1042 0x06 Printing & Imaging
+T1040D4RDB T1040 0x66 Networking
+T1042D4RDB T1042 0x86 Networking
+
+
T1040 SoC Overview
------------------
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
T1040 SoC Personalities
-------------------------
-
T1022 Personality:
T1022 is a reduced personality of T1040 with less core/clusters.
Commands for switching to alternate bank.
1. To change from vbank0 to vbank4
- => qixis_reset altbank (it will boot using vbank4)
+ => cpld reset altbank (it will boot using vbank4)
2.To change from vbank4 to vbank0
- => qixis reset (it will boot using vbank0)
+ => cpld reset (it will boot using vbank0)
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during boot :-
+ -----------------------------------------------
+ Area | Address |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB) |
+ headers | |
+ -----------------------------------------------
+ GD, BD | 0xFFFC8000 (4KB) |
+ -----------------------------------------------
+ ENV | 0xFFFC9000 (8KB) |
+ -----------------------------------------------
+ HEAP | 0xFFFCB000 (30KB) |
+ -----------------------------------------------
+ STACK | 0xFFFD8000 (22KB) |
+ -----------------------------------------------
+ U-boot SPL | 0xFFFD8000 (160KB) |
+ -----------------------------------------------
+
+NAND Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x180000 0x19FFFF u-boot env 128KB
+0x280000 0x29FFFF FMAN Ucode 128KB
+0x380000 0x39FFFF QE Firmware 128KB
+
+SD Card memory Map on T104xRDB
+------------------------------------------
+ Block #blocks Definition Size
+0x008 2048 u-boot 1MB
+0x800 0024 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+SPI Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+Please note QE Firmware is only valid for T1040RDB
+
+
+Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
+==========================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111011
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111011
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111011
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111011
+SW3: 11100001
+
+Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
+=============================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111001
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
+
+PBL-based image generation
+==========================
+Changes only the required register bit in in PBI commands.
+
+Provides reference code which might needs some
+modification as per requirement.
+example:
+By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
+which needs to be changed for SPI and SD.
+
+For SD-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 6c027000 01000000
+
+2. SD does not support flush so remove flush from pbl, make changes in
+ tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+ with 0x091380c0
+
+For SPI-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 5c027000 01000000
+
+2. SPI does not support flush so remove flush from pbl, make changes in
+ tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+ with 0x091380c0
projects / oweals / u-boot.git / blobdiff