+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
+#include <init.h>
+#include <log.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include <linux/delay.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x69;
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
}
-phys_size_t initdram(int board_type)
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
+int dram_init(void)
{
phys_size_t dram_size;
dram_size *= 0x100000;
puts(" DDR: ");
- return dram_size;
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
+ gd->ram_size = dram_size;
+
+ return 0;
}