powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
[oweals/u-boot.git] / board / freescale / t102xrdb / eth_t102xrdb.c
index 856ec6e227961d3be13f745ad55ffd82b8e45673..c06d1b8e0ea4fc77884614e909ddbbc4cc104d11 100644 (file)
@@ -21,7 +21,7 @@
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 #include "../common/fman.h"
 
@@ -58,7 +58,7 @@ int board_eth_init(bd_t *bis)
        fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
        switch (srds_s1) {
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
        case 0x95:
                /* set the on-board RGMII2  PHY */
                fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -73,7 +73,7 @@ int board_eth_init(bd_t *bis)
        case 0x135:
                /* set the on-board 2.5G SGMII AQR105 PHY */
                fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
                /* set the on-board 1G SGMII RTL8211F PHY */
                fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
 #endif
@@ -92,9 +92,9 @@ int board_eth_init(bd_t *bis)
                        fm_info_set_mdio(i, dev);
                        break;
                case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_T1023RDB)
+#if defined(CONFIG_TARGET_T1023RDB)
                        dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
                        dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 #endif
                        fm_info_set_mdio(i, dev);
@@ -128,7 +128,7 @@ int board_eth_init(bd_t *bis)
 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                              enum fm_port port, int offset)
 {
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
        if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
             (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
                        (port == FM1_DTSEC3)) {