avr32: delete non generic board favr-32-ezkit

[oweals/u-boot.git] / board / freescale / p2041rdb / p2041rdb.c

diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 08d10bc9c832f0e5b60532ed18e6c0b310a24484..e600bdbc2a87a38ab014d268aac95cbcfd733ed3 100644 (file)
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -28,7 +28,6 @@ int checkboard(void)
 {
        u8 sw;
        struct cpu_type *cpu = gd->arch.cpu;
-       ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
        unsigned int i;
 
        printf("Board: %sRDB, ", cpu->name);
@@ -38,20 +37,6 @@ int checkboard(void)
        sw = CPLD_READ(fbank_sel);
        printf("vBank: %d\n", sw & 0x1);
 
-       /*
-        * Display the RCW, so that no one gets confused as to what RCW
-        * we're actually using for this boot.
-        */
-       puts("Reset Configuration Word (RCW):");
-       for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-               u32 rcw = in_be32(&gur->rcwsr[i]);
-
-               if ((i % 4) == 0)
-                       printf("\n       %08x:", i * 4);
-               printf(" %08x", rcw);
-       }
-       puts("\n");
-
        /*
         * Display the actual SERDES reference clocks as configured by the
         * dip switches on the board.  Note that the SWx registers could
@@ -131,7 +116,7 @@ void board_config_lanes_mux(void)
 int board_early_init_r(void)
 {
        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+       int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
        /*
         * Remap Boot flash + PROMJET region to caching-inhibited
@@ -142,8 +127,14 @@ int board_early_init_r(void)
        flush_dcache();
        invalidate_icache();
 
-       /* invalidate existing TLB entry for flash + promjet */
-       disable_tlb(flash_esel);
+       if (flash_esel == -1) {
+               /* very unlikely unless something is messed up */
+               puts("Error: Could not find TLB for FLASH BASE\n");
+               flash_esel = 2; /* give our best effort to continue */
+       } else {
+               /* invalidate existing TLB entry for flash + promjet */
+               disable_tlb(flash_esel);
+       }
 
        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -170,20 +161,6 @@ unsigned long get_board_sys_clk(unsigned long dummy)
        }
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-       switch (clock) {
-       case SRDS_PLLCR0_RFCK_SEL_100:
-               return "100";
-       case SRDS_PLLCR0_RFCK_SEL_125:
-               return "125";
-       case SRDS_PLLCR0_RFCK_SEL_156_25:
-               return "156.25";
-       default:
-               return "150";
-       }
-}
-
 #define NUM_SRDS_BANKS 2
 
 int misc_init_r(void)
@@ -238,7 +215,7 @@ int misc_init_r(void)
        return 0;
 }
 
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
        phys_addr_t base;
        phys_size_t size;
@@ -262,4 +239,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
        fdt_fixup_fman_ethernet(blob);
 #endif
+
+       return 0;
 }