Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[oweals/u-boot.git] / board / freescale / p1_p2_rdb / ddr.c

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 9518392cddb7f327c292fb089070718ea1a9a1ec..37c4b0a3ba939bc8317b72fe700ad0f8358eff99 100644 (file)
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -23,10 +23,13 @@
 #include <common.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                                   unsigned int ctrl_num);
 
@@ -43,7 +46,6 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
 #define CONFIG_SYS_DDR_ZQ_CONTROL      0x00000000
 #define CONFIG_SYS_DDR_WRLVL_CONTROL   0x00000000
-#define CONFIG_SYS_DDR_PD_CONTROL      0x00000000
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
@@ -110,7 +112,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -138,7 +139,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -166,7 +166,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -194,7 +193,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
        .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
        .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
        .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
-       .ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
        .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
        .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
        .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
@@ -208,24 +206,40 @@ phys_size_t fixed_sdram (void)
 {
        sys_info_t sysinfo;
        char buf[32];
+       fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+       size_t ddr_size;
+       struct cpu_type *cpu;
 
        get_sys_info(&sysinfo);
        printf("Configuring DDR for %s MT/s data rate\n",
                                strmhz(buf, sysinfo.freqDDRBus));
 
        if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
-               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
+               ddr_cfg_regs = &ddr_cfg_regs_400;
        else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
-               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
+               ddr_cfg_regs = &ddr_cfg_regs_533;
        else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
-               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
+               ddr_cfg_regs = &ddr_cfg_regs_667;
        else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
-               fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
+               ddr_cfg_regs = &ddr_cfg_regs_800;
        else
                panic("Unsupported DDR data rate %s MT/s data rate\n",
                                        strmhz(buf, sysinfo.freqDDRBus));
 
-       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+       cpu = gd->cpu;
+       /* P1020 and it's derivatives support max 32bit DDR width */
+       if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+               cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+               ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+               ddr_cfg_regs->cs[0].bnds = 0x0000001F;
+               ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+       }
+       else
+               ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+       fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+
+       return ddr_size;
 }
 
 phys_size_t initdram(int board_type)