mx6: Avoid writing to read-only bits in imximage.cfg
[oweals/u-boot.git] / board / freescale / p1022ds / p1022ds.c
index 8ef627fc7b452cbf64b67f59ef5b80b25f7a547b..aca30f368070e2010278b0084063759e77277369 100644 (file)
@@ -56,12 +56,8 @@ int checkboard(void)
 {
        u8 sw;
 
-       puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
-       puts("(36-bit addrmap) ");
-#endif
-
-       printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+       printf("Board: P1022DS Sys ID: 0x%02x, "
+              "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
                in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
        sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
@@ -308,7 +304,8 @@ int board_eth_init(bd_t *bis)
  * ft_codec_setup - fix up the clock-frequency property of the codec node
  *
  * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ * hwconfig option.  If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
  */
 static void ft_codec_setup(void *blob, const char *compatible)
 {
@@ -317,12 +314,15 @@ static void ft_codec_setup(void *blob, const char *compatible)
        u32 freq;
 
        audclk = hwconfig_arg("audclk", &arglen);
-       if (audclk && (strncmp(audclk, "11", 2) == 0))
-               freq = 11289600;
-       else
-               freq = 12288000;
+       if (audclk) {
+               if (strncmp(audclk, "11", 2) == 0)
+                       freq = 11289600;
+               else
+                       freq = 12288000;
 
-       do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+               do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+                                      freq, 1);
+       }
 }
 
 void ft_board_setup(void *blob, bd_t *bd)