mx6: Avoid writing to read-only bits in imximage.cfg

[oweals/u-boot.git] / board / freescale / p1022ds / p1022ds.c

diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 8b78404b85d2ae04c5aa031decf4fd88288fb93b..aca30f368070e2010278b0084063759e77277369 100644 (file)
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -22,6 +22,7 @@
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fsl_mdio.h>
 #include <tsec.h>
 #include <asm/fsl_law.h>
 #include <netdev.h>
@@ -45,6 +46,9 @@ int board_early_init_f(void)
        /* Set the pin muxing to enable ETSEC2. */
        clrbits_be32(&gur->pmuxcr2, 0x001F8000);
 
+       /* Enable the SPI */
+       clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+
        return 0;
 }
 
@@ -52,12 +56,8 @@ int checkboard(void)
 {
        u8 sw;
 
-       puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
-       puts("(36-bit addrmap) ");
-#endif
-
-       printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+       printf("Board: P1022DS Sys ID: 0x%02x, "
+              "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
                in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
        sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
@@ -279,6 +279,7 @@ int board_early_init_r(void)
  */
 int board_eth_init(bd_t *bis)
 {
+       struct fsl_pq_mdio_info mdio_info;
        struct tsec_info_struct tsec_info[2];
        unsigned int num = 0;
 
@@ -291,6 +292,10 @@ int board_eth_init(bd_t *bis)
        num++;
 #endif
 
+       mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+       mdio_info.name = DEFAULT_MII_NAME;
+       fsl_pq_mdio_init(bis, &mdio_info);
+
        return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
 }
 
@@ -299,7 +304,8 @@ int board_eth_init(bd_t *bis)
  * ft_codec_setup - fix up the clock-frequency property of the codec node
  *
  * Update the clock-frequency property based on the value of the 'audclk'
- * hwconfig option.  If audclk is not specified, then default to 12.288MHz.
+ * hwconfig option.  If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
  */
 static void ft_codec_setup(void *blob, const char *compatible)
 {
@@ -308,12 +314,15 @@ static void ft_codec_setup(void *blob, const char *compatible)
        u32 freq;
 
        audclk = hwconfig_arg("audclk", &arglen);
-       if (audclk && (strncmp(audclk, "11", 2) == 0))
-               freq = 11289600;
-       else
-               freq = 12288000;
+       if (audclk) {
+               if (strncmp(audclk, "11", 2) == 0)
+                       freq = 11289600;
+               else
+                       freq = 12288000;
 
-       do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1);
+               do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+                                      freq, 1);
+       }
 }
 
 void ft_board_setup(void *blob, bd_t *bd)