Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / board / freescale / mx6sabreauto / mx6sabreauto.c

diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index bfd5ffa5c7ce72799db97eab466f5e8fa396d5b8..bdeb5f7667343622116d4100f6baac8d3454971e 100644 (file)
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -24,6 +24,7 @@
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/mach-imx/video.h>
 #include <asm/arch/crm_regs.h>
@@ -433,6 +434,39 @@ u32 get_board_rev(void)
        return (get_cpu_rev() & ~(0xF << 8)) | rev;
 }
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+       unsigned short val;
+
+       /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+       val &= 0xffe3;
+       val |= 0x18;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+       /* introduce tx clock delay */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+       val |= 0x0100;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       ar8031_phy_fixup(phydev);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
@@ -654,14 +688,14 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-       setenv("board_name", "SABREAUTO");
+       env_set("board_name", "SABREAUTO");
 
        if (is_mx6dqp())
-               setenv("board_rev", "MX6QP");
+               env_set("board_rev", "MX6QP");
        else if (is_mx6dq())
-               setenv("board_rev", "MX6Q");
+               env_set("board_rev", "MX6Q");
        else if (is_mx6sdl())
-               setenv("board_rev", "MX6DL");
+               env_set("board_rev", "MX6DL");
 #endif
 
        return 0;
@@ -745,6 +779,13 @@ int board_ehci_power(int port, int on)
 #include <spl.h>
 #include <libfdt.h>
 
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+       return 0;
+}
+#endif
+
 static void ccgr_init(void)
 {
        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -758,23 +799,6 @@ static void ccgr_init(void)
        writel(0x000003FF, &ccm->CCGR6);
 }
 
-static void gpr_init(void)
-{
-       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-       /* enable AXI cache for VDOA/VPU/IPU */
-       writel(0xF00000CF, &iomux->gpr[4]);
-       if (is_mx6dqp()) {
-               /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-               writel(0x007F007F, &iomux->gpr[6]);
-               writel(0x007F007F, &iomux->gpr[7]);
-       } else {
-               /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-               writel(0x007F007F, &iomux->gpr[6]);
-               writel(0x007F007F, &iomux->gpr[7]);
-       }
-}
-
 static int mx6q_dcd_table[] = {
        0x020e0798, 0x000C0000,
        0x020e0758, 0x00000000,