common/board_f.c: modify the macro to use get_clocks() more common

[oweals/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 59387ffaaa7e7960e625f3b8e0833f7f297dee23..7c0e90ad0bc0f866b1c32fde76866e385523ee24 100644 (file)
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -29,6 +29,7 @@
 #include <asm/arch/crm_regs.h>
 #include <pca953x.h>
 #include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -311,30 +312,9 @@ static void setup_gpmi_nand(void)
        /* config gpmi nand iomux */
        imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
 
-       /* gate ENFC_CLK_ROOT clock first,before clk source switch */
-       clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-       clrbits_le32(&mxc_ccm->CCGR4,
-               MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
-
-       /* config gpmi and bch clock to 100 MHz */
-       clrsetbits_le32(&mxc_ccm->cs2cdr,
-                       MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-                       MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-                       MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-                       MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+       setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
                        MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-                       MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-       /* enable ENFC_CLK_ROOT clock */
-       setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
-       /* enable gpmi and bch clock gating */
-       setbits_le32(&mxc_ccm->CCGR4,
-                    MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-                    MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+                       MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
 
        /* enable apbh clock gating */
        setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
@@ -374,9 +354,22 @@ int board_phy_config(struct phy_device *phydev)
        return 0;
 }
 
-int board_eth_init(bd_t *bis)
+static void setup_fec(void)
 {
+       if (is_mx6dqp()) {
+               /*
+                * select ENET MAC0 TX clock from PLL
+                */
+               imx_iomux_set_gpr_register(5, 9, 1, 1);
+               enable_fec_anatop_clock(0, ENET_125MHZ);
+       }
+
        setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+       setup_fec();
 
        return cpu_eth_init(bis);
 }
@@ -515,12 +508,21 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
 int power_init_board(void)
 {
        struct pmic *p;
+       unsigned int value;
 
        p = pfuze_common_init(I2C_PMIC);
        if (!p)
                return -ENODEV;
 
-       return 0;
+       if (is_mx6dqp()) {
+               /* set SW2 staby volatage 0.975V*/
+               pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+               value &= ~0x3f;
+               value |= 0x17;
+               pmic_reg_write(p, PFUZE100_SW2STBY, value);
+       }
+
+       return pfuze_mode_init(p, APS_PFM);
 }
 
 #ifdef CONFIG_CMD_BMODE
@@ -537,6 +539,17 @@ int board_late_init(void)
        add_board_boot_modes(board_boot_modes);
 #endif
 
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+       setenv("board_name", "SABREAUTO");
+
+       if (is_mx6dqp())
+               setenv("board_rev", "MX6QP");
+       else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+               setenv("board_rev", "MX6Q");
+       else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+               setenv("board_rev", "MX6DL");
+#endif
+
        return 0;
 }