#include <common.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
static void power_init(void)
{
unsigned int val;
- unsigned int reg;
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
/* Write needed to Power Gate 2 register */
pmic_reg_write(REG_MODE_1, val);
udelay(200);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; /* Lower reset line */
- writel(reg, GPIO2_BASE_ADDR + 0x0);
-
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; /* configure GPIO lines as output */
- writel(reg, GPIO2_BASE_ADDR + 0x4);
+ gpio_direction_output(46, 0);
/* Reset the ethernet controller over GPIO */
writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
udelay(500);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ gpio_set_value(46, 1);
}
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = readl(GPIO1_BASE_ADDR) & 0x01;
+ *cd = gpio_get_value(0);
else
- *cd = readl(GPIO1_BASE_ADDR) & 0x40;
+ *cd = gpio_get_value(6);
return 0;
}
int checkboard(void)
{
- puts("Board: MX51EVK ");
-
- switch (system_rev & 0xff) {
- case CHIP_REV_3_0:
- puts("3.0 [");
- break;
- case CHIP_REV_2_5:
- puts("2.5 [");
- break;
- case CHIP_REV_2_0:
- puts("2.0 [");
- break;
- case CHIP_REV_1_1:
- puts("1.1 [");
- break;
- case CHIP_REV_1_0:
- default:
- puts("1.0 [");
- break;
- }
+ puts("Board: MX51EVK\n");
- switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
- case 0x0001:
- puts("POR");
- break;
- case 0x0009:
- puts("RST");
- break;
- case 0x0010:
- case 0x0011:
- puts("WDOG");
- break;
- default:
- puts("unknown");
- }
- puts("]\n");
return 0;
}