#include <i2c.h>
#include <pmic.h>
#include <fsl_pmic.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
#include <mc9sdz60.h>
#include <mc13892.h>
#include <linux/types.h>
/* enable clocks */
writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |
- MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
MXC_CCM_CGR0_EPIT1_MASK,
&ccm->cgr0);
val |= 0x80;
mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
- return 0;
-}
-
-int checkboard(void)
-{
- struct ccm_regs *ccm =
- (struct ccm_regs *)IMX_CCM_BASE;
- u32 cpu_rev = get_cpu_rev();
-
- /*
- * Be sure that I2C is initialized to check
- * the board revision
- */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
/* Print board revision */
- printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F);
-
- /* Print CPU revision */
- printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F);
-
- switch (readl(&ccm->rcsr) & 0x0F) {
- case 0x0000:
- puts("POR");
- break;
- case 0x0002:
- puts("JTAG");
- break;
- case 0x0004:
- puts("RST");
- break;
- case 0x0008:
- puts("WDT");
- break;
- default:
- puts("unknown");
- }
- puts("]\n");
+ printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
return 0;
}
return rc;
}
+
+#if defined(CONFIG_FSL_ESDHC)
+
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ /* configure pins for SDHC1 only */
+ mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
+}
+#endif