#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+#define FEC_RESET_B IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
#define CARD_DETECT IMX_GPIO_NR(2, 1)
DECLARE_GLOBAL_DATA_PTR;
};
#endif
+static void mx25pdk_fec_init(void)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+ /* FEC pin init is generic */
+ mx25_fec_init_pins();
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ /*
+ * Set up FEC_RESET_B and FEC_ENABLE_B
+ *
+ * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+ * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+ */
+ writel(gpio_mux_mode, &muxctl->pad_d12);
+ writel(gpio_mux_mode, &muxctl->pad_a17);
+
+ writel(0x0, &padctl->pad_d12);
+ writel(0x0, &padctl->pad_a17);
+
+ /* Assert RESET and ENABLE low */
+ gpio_direction_output(FEC_RESET_B, 0);
+ gpio_direction_output(FEC_ENABLE_B, 0);
+
+ udelay(10);
+
+ /* Deassert RESET and ENABLE */
+ gpio_set_value(FEC_RESET_B, 1);
+ gpio_set_value(FEC_ENABLE_B, 1);
+
+ /* Setup I2C pins so that PMIC can turn on PHY supply */
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+ writel(0x1E8, &padctl->pad_i2c1_clk);
+ writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
return 0;
}
+int board_late_init(void)
+{
+ struct pmic *p;
+ int ret;
+
+ mx25pdk_fec_init();
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* Turn on Ethernet PHY supply */
+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+ return 0;
+}
+
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{