#include "../common/pixis.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-long int fixed_sdram(void);
+phys_size_t fixed_sdram(void);
int board_early_init_f(void)
{
phys_size_t
initdram(int board_type)
{
- long dram_size = 0;
+ phys_size_t dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
return dram_size;
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
puts(" DDR: ");
return dram_size;
}
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
-long int
+phys_size_t
fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc86xxcts_config_table
-#endif
-};
+static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
-#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pci1_hose;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
-
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
+ int off;
+ u64 *tmp;
+ u32 *addrcells;
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
+
+ /*
+ * Warn if it looks like the device tree doesn't match u-boot.
+ * This is just an estimation, based on the location of CCSR,
+ * which is defined by the "reg" property in the soc node.
+ */
+ off = fdt_path_offset(blob, "/soc8641");
+ addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+ if (tmp) {
+ u64 addr;
+ if (addrcells && (*addrcells == 1))
+ addr = *(u32 *)tmp;
+ else
+ addr = *tmp;
+
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+ printf("WARNING: The CCSRBAR address in your .dts "
+ "does not match the address of the CCSR "
+ "in u-boot. This means your .dts might "
+ "be old.\n");
}
}
#endif