Merge branch 'master' of git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / board / freescale / mpc8641hpcn / mpc8641hpcn.c

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 15be0c6134a2a0e0c7dd1875ea2ef502ed0654b8..a8b2112264e2494242783d0b3c95fe1743234801 100644 (file)
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -24,7 +24,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <libfdt.h>
@@ -42,10 +42,23 @@ int board_early_init_f(void)
 
 int checkboard(void)
 {
-       printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
-               "System Version: 0x%02x, FPGA Version: 0x%02x\n",
-               in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-               in8(PIXIS_BASE + PIXIS_PVER));
+       u8 vboot;
+       u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+       printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
+               "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+               in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+               in_8(pixis_base + PIXIS_PVER));
+
+       vboot = in_8(pixis_base + PIXIS_VBOOT);
+       if (vboot & PIXIS_VBOOT_FMAP)
+               printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+       else
+               puts ("Promjet\n");
+
+#ifdef CONFIG_PHYS_64BIT
+       printf ("       36-bit physical address map\n");
+#endif
        return 0;
 }
 
@@ -88,7 +101,7 @@ fixed_sdram(void)
        ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
        ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
@@ -106,9 +119,9 @@ fixed_sdram(void)
 
 #if defined (CONFIG_DDR_ECC)
        /* Enable ECC checking */
-       ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+       ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 #else
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
        ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 #endif
        asm("sync; isync");
@@ -130,9 +143,6 @@ static struct pci_controller pci2_hose;
 
 int first_free_busno = 0;
 
-extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
-extern void fsl_pci_init(struct pci_controller *hose);
-
 void pci_init_board(void)
 {
 #ifdef CONFIG_PCI1
@@ -163,23 +173,23 @@ void pci_init_board(void)
                }
                debug("\n");
 
-               /* inbound */
-               r += fsl_pci_setup_inbound_windows(r);
-
                /* outbound memory */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_MEM_BASE,
+                              CONFIG_SYS_PCI1_MEM_BUS,
                               CONFIG_SYS_PCI1_MEM_PHYS,
                               CONFIG_SYS_PCI1_MEM_SIZE,
                               PCI_REGION_MEM);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
 
+               /* inbound */
+               r += fsl_pci_setup_inbound_windows(r);
+
                hose->region_count = r - hose->regions;
 
                hose->first_busno=first_free_busno;
@@ -195,7 +205,7 @@ void pci_init_board(void)
                 * Activate ULI1575 legacy chip by performing a fake
                 * memory access.  Needed to make ULI RTC work.
                 */
-               in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
+               in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
                                       + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
 
        } else {
@@ -212,23 +222,23 @@ void pci_init_board(void)
        struct pci_controller *hose = &pci2_hose;
        struct pci_region *r = hose->regions;
 
-       /* inbound */
-       r += fsl_pci_setup_inbound_windows(r);
-
        /* outbound memory */
        pci_set_region(r++,
-                      CONFIG_SYS_PCI2_MEM_BASE,
+                      CONFIG_SYS_PCI2_MEM_BUS,
                       CONFIG_SYS_PCI2_MEM_PHYS,
                       CONFIG_SYS_PCI2_MEM_SIZE,
                       PCI_REGION_MEM);
 
        /* outbound io */
        pci_set_region(r++,
-                      CONFIG_SYS_PCI2_IO_BASE,
+                      CONFIG_SYS_PCI2_IO_BUS,
                       CONFIG_SYS_PCI2_IO_PHYS,
                       CONFIG_SYS_PCI2_IO_SIZE,
                       PCI_REGION_IO);
 
+       /* inbound */
+       r += fsl_pci_setup_inbound_windows(r);
+
        hose->region_count = r - hose->regions;
 
        hose->first_busno=first_free_busno;
@@ -248,12 +258,13 @@ void pci_init_board(void)
 
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
-                       struct pci_controller *hose);
-
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
+       int off;
+       u64 *tmp;
+       u32 *addrcells;
+
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_PCI1
@@ -262,6 +273,29 @@ ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCI2
        ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 #endif
+
+       /*
+        * Warn if it looks like the device tree doesn't match u-boot.
+        * This is just an estimation, based on the location of CCSR,
+        * which is defined by the "reg" property in the soc node.
+        */
+       off = fdt_path_offset(blob, "/soc8641");
+       addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+       tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+       if (tmp) {
+               u64 addr;
+               if (addrcells && (*addrcells == 1))
+                       addr = *(u32 *)tmp;
+               else
+                       addr = *tmp;
+
+               if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+                       printf("WARNING: The CCSRBAR address in your .dts "
+                              "does not match the address of the CCSR "
+                              "in u-boot.  This means your .dts might "
+                              "be old.\n");
+       }
 }
 #endif
 
@@ -276,11 +310,12 @@ get_board_sys_clk(ulong dummy)
 {
        u8 i, go_bit, rd_clks;
        ulong val = 0;
+       u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-       go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+       go_bit = in_8(pixis_base + PIXIS_VCTL);
        go_bit &= 0x01;
 
-       rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+       rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
        rd_clks &= 0x1C;
 
        /*
@@ -291,11 +326,11 @@ get_board_sys_clk(ulong dummy)
 
        if (go_bit) {
                if (rd_clks == 0x1c)
-                       i = in8(PIXIS_BASE + PIXIS_AUX);
+                       i = in_8(pixis_base + PIXIS_AUX);
                else
-                       i = in8(PIXIS_BASE + PIXIS_SPD);
+                       i = in_8(pixis_base + PIXIS_SPD);
        } else {
-               i = in8(PIXIS_BASE + PIXIS_SPD);
+               i = in_8(pixis_base + PIXIS_SPD);
        }
 
        i &= 0x07;
@@ -336,3 +371,22 @@ int board_eth_init(bd_t *bis)
        cpu_eth_init(bis);
        return pci_eth_init(bis);
 }
+
+void board_reset(void)
+{
+       u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+       out_8(pixis_base + PIXIS_RST, 0);
+
+       while (1)
+               ;
+}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+       cpu_mp_lmb_reserve(lmb);
+}
+#endif