Merge branch 'master' of git://www.denx.de/git/u-boot-mips

[oweals/u-boot.git] / board / freescale / mpc8610hpcd / mpc8610hpcd.c

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 16acbbe8ad52b61767c0b2166b56a011f8f6b903..ce563dc67a996d018c3f1c435115d28bacc59bbc 100644 (file)
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -27,10 +27,10 @@
 #include <asm/immap_86xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <i2c.h>
-#include <spd.h>
 #include <asm/io.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <spd_sdram.h>
 
 #include "../common/pixis.h"
 
@@ -38,10 +38,6 @@
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
 void sdram_init(void);
 long int fixed_sdram(void);
 void mpc8610hpcd_diu_init(void);
@@ -145,42 +141,6 @@ initdram(int board_type)
 }
 
 
-#if defined(CFG_DRAM_TEST)
-int
-testdram(void)
-{
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
-       uint *p;
-
-       puts("SDRAM test phase 1:\n");
-       for (p = pstart; p < pend; p++)
-               *p = 0xaaaaaaaa;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0xaaaaaaaa) {
-                       printf("SDRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-
-       puts("SDRAM test phase 2:\n");
-       for (p = pstart; p < pend; p++)
-               *p = 0x55555555;
-
-       for (p = pstart; p < pend; p++) {
-               if (*p != 0x55555555) {
-                       printf("SDRAM test fails at: %08x\n", (uint) p);
-                       return 1;
-               }
-       }
-
-       puts("SDRAM test passed.\n");
-       return 0;
-}
-#endif
-
-
 #if !defined(CONFIG_SPD_EEPROM)
 /*
  * Fixed sdram init -- doesn't use serial presence detect.
@@ -196,7 +156,7 @@ long int fixed_sdram(void)
        ddr->cs0_bnds = 0x0000001f;
        ddr->cs0_config = 0x80010202;
 
-       ddr->ext_refrec = 0x00000000;
+       ddr->timing_cfg_3 = 0x00000000;
        ddr->timing_cfg_0 = 0x00260802;
        ddr->timing_cfg_1 = 0x3935d322;
        ddr->timing_cfg_2 = 0x14904cc8;