Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[oweals/u-boot.git] / board / freescale / mpc8572ds / mpc8572ds.c

diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 4733b82f0558a278a1a598c4cf4e7d7fb61f0e73..4b956171fe7f12025471ccfd8d3def088f3f3d66 100644 (file)
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -27,7 +27,7 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <miiphy.h>
@@ -42,8 +42,12 @@ long int fixed_sdram(void);
 
 int checkboard (void)
 {
-       printf ("Board: MPC8572DS, System ID: 0x%02x, "
-               "System Version: 0x%02x, FPGA Version: 0x%02x\n",
+       puts ("Board: MPC8572DS ");
+#ifdef CONFIG_PHYS_64BIT
+       puts ("(36-bit addrmap) ");
+#endif
+       printf ("Sys ID: 0x%02x, "
+               "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
                in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
                in8(PIXIS_BASE + PIXIS_PVER));
        return 0;
@@ -135,9 +139,6 @@ static struct pci_controller pcie2_hose;
 static struct pci_controller pcie3_hose;
 #endif
 
-extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
-extern void fsl_pci_init(struct pci_controller *hose);
-
 int first_free_busno=0;
 #ifdef CONFIG_PCI
 void pci_init_board(void)
@@ -170,7 +171,7 @@ void pci_init_board(void)
                struct pci_region *r = hose->regions;
                u32 temp32;
 
-               if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+               if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
                        printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
                                        pcie_ep ? "End Point" : "Root Complex",
                                        (uint)pci);
@@ -185,14 +186,14 @@ void pci_init_board(void)
 
                        /* outbound memory */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE3_MEM_BASE,
+                                       CONFIG_SYS_PCIE3_MEM_BUS,
                                        CONFIG_SYS_PCIE3_MEM_PHYS,
                                        CONFIG_SYS_PCIE3_MEM_SIZE,
                                        PCI_REGION_MEM);
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE3_IO_BASE,
+                                       CONFIG_SYS_PCIE3_IO_BUS,
                                        CONFIG_SYS_PCIE3_IO_PHYS,
                                        CONFIG_SYS_PCIE3_IO_SIZE,
                                        PCI_REGION_IO);
@@ -215,9 +216,11 @@ void pci_init_board(void)
 
                        pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
                                        PCI_BASE_ADDRESS_1, &temp32);
-                       if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
-                               debug(" uli1572 read to %x\n", temp32);
-                               in_be32((unsigned *)temp32);
+                       if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+                               void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+                                                               temp32, 4, 0);
+                               debug(" uli1572 read to %p\n", p);
+                               in_be32(p);
                        }
                } else {
                        printf ("    PCIE3: disabled\n");
@@ -237,7 +240,7 @@ void pci_init_board(void)
                int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
                struct pci_region *r = hose->regions;
 
-               if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+               if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
                        printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
                                        pcie_ep ? "End Point" : "Root Complex",
                                        (uint)pci);
@@ -252,14 +255,14 @@ void pci_init_board(void)
 
                        /* outbound memory */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE2_MEM_BASE,
+                                       CONFIG_SYS_PCIE2_MEM_BUS,
                                        CONFIG_SYS_PCIE2_MEM_PHYS,
                                        CONFIG_SYS_PCIE2_MEM_SIZE,
                                        PCI_REGION_MEM);
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE2_IO_BASE,
+                                       CONFIG_SYS_PCIE2_IO_BUS,
                                        CONFIG_SYS_PCIE2_IO_PHYS,
                                        CONFIG_SYS_PCIE2_IO_SIZE,
                                        PCI_REGION_IO);
@@ -307,14 +310,14 @@ void pci_init_board(void)
 
                        /* outbound memory */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE1_MEM_BASE,
+                                       CONFIG_SYS_PCIE1_MEM_BUS,
                                        CONFIG_SYS_PCIE1_MEM_PHYS,
                                        CONFIG_SYS_PCIE1_MEM_SIZE,
                                        PCI_REGION_MEM);
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE1_IO_BASE,
+                                       CONFIG_SYS_PCIE1_IO_BUS,
                                        CONFIG_SYS_PCIE1_IO_PHYS,
                                        CONFIG_SYS_PCIE1_IO_SIZE,
                                        PCI_REGION_IO);
@@ -358,7 +361,7 @@ int board_early_init_r(void)
        /* invalidate existing TLB entry for flash + promjet */
        disable_tlb(flash_esel);
 
-       set_tlb(1, flashbase, flashbase,                /* tlb, epn, rpn */
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
                        0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 
@@ -540,7 +543,9 @@ int board_eth_init(bd_t *bis)
                return 0;
        }
 
+#ifdef CONFIG_FSL_SGMII_RISER
        fsl_sgmii_riser_init(tsec_info, num);
+#endif
 
        tsec_eth_init(bis, tsec_info, num);
 
@@ -549,12 +554,10 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
-                       struct pci_controller *hose);
-
 void ft_board_setup(void *blob, bd_t *bd)
 {
-       ulong base, size;
+       phys_addr_t base;
+       phys_size_t size;
 
        ft_cpu_setup(blob, bd);
 
@@ -572,6 +575,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCIE1
        ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 #endif
+#ifdef CONFIG_FSL_SGMII_RISER
+       fsl_sgmii_riser_fdt_fixup(blob);
+#endif
 }
 #endif