#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <tsec.h>
#include "../common/pixis.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
+#include "../common/sgmii_riser.h"
long int fixed_sdram(void);
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
puts(" DDR: ");
return dram_size;
}
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
- int pcie_configured = io_sel >= 1;
+ int pcie_configured = (io_sel == 0x7);
+ struct pci_region *r = hose->regions;
u32 temp32;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
- (host_agent == 6);
- int pcie_configured = io_sel & 4;
+ (host_agent == 6) || (host_agent == 0);
+ int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
+ int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
- int pcie_configured = io_sel & 6;
+ int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
+ (io_sel == 0x7) || (io_sel == 0xb) ||
+ (io_sel == 0xc) || (io_sel == 0xf);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
int board_early_init_r(void)
{
- unsigned int i;
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = 2;
* so that flash can be erased properly.
*/
- /* Invalidate any remaining lines of the flash from caches. */
- for (i = 0; i < 256*1024*1024; i+=32) {
- asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i));
- asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i));
- }
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
#endif
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct tsec_info_struct tsec_info[4];
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+#ifdef CONFIG_TSEC4
+ SET_STD_TSEC_INFO(tsec_info[num], 4);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+ fsl_sgmii_riser_init(tsec_info, num);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
ulong base, size;
ft_cpu_setup(blob, bd);
fdt_fixup_memory(blob, (u64)base, (u64)size);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
- }
}
#endif
projects / oweals / u-boot.git / blobdiff