{0, 25, 1, 0, 1}, /* QEUART_RTS */
{1, 23, 2, 0, 1}, /* QEUART_CTS */
+ /* QE USB */
+ {5, 3, 1, 0, 1}, /* USB_OE */
+ {5, 4, 1, 0, 2}, /* USB_TP */
+ {5, 5, 1, 0, 2}, /* USB_TN */
+ {5, 6, 2, 0, 2}, /* USB_RP */
+ {5, 7, 2, 0, 1}, /* USB_RX */
+ {5, 8, 2, 0, 1}, /* USB_RN */
+ {2, 4, 2, 0, 2}, /* CLK5 */
+
/* SPI Flash, M25P40 */
{4, 27, 3, 0, 1}, /* SPI_MOSI */
{4, 28, 3, 0, 1}, /* SPI_MISO */
console_assign(stdin, "eserial1");
printf("Switched to UART1 (initial log has been printed to "
"UART0).\n");
+
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
+ PLPPAR1_ESDHC_4BITS_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
+ PLPDIR1_ESDHC_4BITS_VAL);
bcsr6 |= BCSR6_SD_CARD_4BITS;
} else {
printf("should be disabled.\n");
break;
}
}
+
+ if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
+ if (off < 0) {
+ printf("WARNING: could not find esdhc node\n");
+ return;
+ }
+ fdt_delprop(blob, off, "sdhci,1-bit-only");
+ }
}
#else
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
#endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
-int first_free_busno = 0;
-
-#ifdef CONFIG_PCI
-void
-pci_init_board(void)
+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
{
- volatile ccsr_gur_t *gur;
- uint io_sel;
- uint host_agent;
-
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
-#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci;
- struct pci_controller *hose;
- int pcie_ep;
- struct pci_region *r;
- int pcie_configured;
-
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- r = hose->regions;
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
+ clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+ else
+ setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
+ if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
+ clrbits_8(&bcsr[17], BCSR17_USBVCC);
+ clrbits_8(&bcsr[17], BCSR17_USBMODE);
+ do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+ } else {
+ setbits_8(&bcsr[17], BCSR17_USBVCC);
+ setbits_8(&bcsr[17], BCSR17_USBMODE);
+ }
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf ("\n");
+ clrbits_8(&bcsr[17], BCSR17_nUSBEN);
+}
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[1];
+ u32 devdisr, pordevsr, io_sel;
+ int first_free_busno = 0;
+ int num = 0;
- hose->region_count = r - hose->regions;
+ int pcie_ep, pcie_configured;
- hose->first_busno=first_free_busno;
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf ("PCIE on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- first_free_busno=hose->last_busno+1;
+#ifdef CONFIG_PCIE1
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf (" PCIE1: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
+
}
#endif /* CONFIG_PCI */
#endif
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
+ fdt_board_fixup_qe_usb(blob, bd);
}
#endif