mpc85xx boards: initdram() cleanup/bugfix

[oweals/u-boot.git] / board / freescale / mpc8569mds / mpc8569mds.c

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 1eddeef37f3b1dd6768492070a145fea8728ab64..07db16aa0c237047a084fc78d16c286325afc4c3 100644 (file)
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor.
+ * Copyright 2009-2010 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -27,9 +27,11 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
 #include <i2c.h>
@@ -43,8 +45,6 @@
 #include "../common/pq-mds-pib.h"
 #endif
 
-phys_size_t fixed_sdram(void);
-
 const qe_iop_conf_t qe_iop_conf_tab[] = {
        /* QE_MUX_MDC */
        {2,  31, 1, 0, 1}, /* QE_MUX_MDC               */
@@ -211,45 +211,36 @@ int board_early_init_f (void)
        return 0;
 }
 
-int checkboard (void)
-{
-       printf ("Board: 8569 MDS\n");
-
-       return 0;
-}
-
-phys_size_t
-initdram(int board_type)
+int board_early_init_r(void)
 {
-       long dram_size = 0;
-
-       puts("Initializing\n");
+       const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+       const u8 flash_esel = 0;
 
-#if defined(CONFIG_DDR_DLL)
        /*
-        * Work around to stabilize DDR DLL MSYNC_IN.
-        * Errata DDR9 seems to have been fixed.
-        * This is now the workaround for Errata DDR11:
-        *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+        * Remap Boot flash to caching-inhibited
+        * so that flash can be erased properly.
         */
-       volatile ccsr_gur_t *gur =
-                       (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
-       out_be32(&gur->ddrdllcr, 0x81000000);
-       udelay(200);
-#endif
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
 
-#ifdef CONFIG_SPD_EEPROM
-       dram_size = fsl_ddr_sdram();
-#else
-       dram_size = fixed_sdram();
-#endif
+       /* invalidate existing TLB entry for flash */
+       disable_tlb(flash_esel);
 
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
+       set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE,     /* tlb, epn, rpn */
+               MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+               0, flash_esel,                          /* ts, esel */
+               BOOKE_PAGESZ_64M, 1);                   /* tsize, iprot */
 
-       puts("    DDR: ");
-       return dram_size;
+       return 0;
+}
+
+int checkboard (void)
+{
+       printf ("Board: 8569 MDS\n");
+
+       return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
@@ -308,7 +299,7 @@ void
 local_bus_init(void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
        uint clkdiv;
        uint lbc_hz;
@@ -553,18 +544,18 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE1
-       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+       pcie_configured = is_serdes_configured(PCIE1);
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-                               pcie_ep ? "Endpoint" : "Root Complex",
-                               pci_info[num].regs);
+               printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
+                       pcie_ep ? "Endpoint" : "Root Complex",
+                       pci_info[num].regs);
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
                                        &pcie1_hose, first_free_busno);
        } else {
-               printf ("    PCIE1: disabled\n");
+               printf("PCIE1: disabled\n");
        }
 
        puts("\n");
@@ -596,8 +587,8 @@ void ft_board_setup(void *blob, bd_t *bd)
                        break;
                }
 
-               err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
-                                       "rmii");
+               err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
+
                if (err < 0) {
                        printf("WARNING: could not set phy-connection-type "
                                "%s.\n", fdt_strerror(err));
@@ -635,9 +626,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
        ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE1
-       ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
-#endif
+       FT_FSL_PCI_SETUP;
+
        fdt_board_fixup_esdhc(blob, bd);
        fdt_board_fixup_qe_uart(blob, bd);
        fdt_board_fixup_qe_usb(blob, bd);