board: ls2080aqds: transition to DM_ETH

[oweals/u-boot.git] / board / freescale / mpc8568mds / bcsr.h

diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
index aefd9bf54d388b94d869b71f1839f27b8c8419d2..a8e13a2a5577951b9033d75e15702c1806e98f97 100644 (file)
--- a/board/freescale/mpc8568mds/bcsr.h
+++ b/board/freescale/mpc8568mds/bcsr.h
@@ -1,23 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2007 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #ifndef __BCSR_H_
@@ -32,8 +15,8 @@
        7       cfg boot seq
 
        * BCSR 1 *
-       0:2     cfg rom lock
-       3:5     cfg host agent
+       0:2     cfg rom lock
+       3:5     cfg host agent
        6       PCI IO
        7       cfg RIO size
 
@@ -46,7 +29,7 @@
        0       TSEC1 reduce
        1       TSEC2 reduce
        2:3     TSEC1 protocol
-       4:5     TSEC2 protocol
+       4:5     TSEC2 protocol
        6       PHY1 slave
        7       PHY2 slave
 
@@ -70,9 +53,9 @@
        7       Power on reset
 
        * BCSR 7 *
-       2       board host mode indication
-       5       enable TSEC1 PHY
-       6       enable TSEC2 PHY
+       2       board host mode indication
+       5       enable TSEC1 PHY
+       6       enable TSEC2 PHY
 
        * BCSR 8 *
        0       UCC GETH1 enable
@@ -90,6 +73,11 @@
        7       Flash write protect
 */
 
+#define BCSR_UCC1_GETH_EN      (0x1 << 7)
+#define BCSR_UCC2_GETH_EN      (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK     (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK     (0x3 << 0)
+
 /*BCSR Utils functions*/
 
 void enable_8568mds_duart(void);
@@ -97,4 +85,8 @@ void enable_8568mds_flash_write(void);
 void disable_8568mds_flash_write(void);
 void enable_8568mds_qe_mdio(void);
 
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
 #endif /* __BCSR_H_ */