powerpc/mpc85xxcds: Fix PCI speed

[oweals/u-boot.git] / board / freescale / mpc8541cds / mpc8541cds.c

diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 59ec60446e91acda15112254ce866f6a83e37793..d127137ddb05f440d334ee6c0c6e6fda8a395683 100644 (file)
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2011 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
 void local_bus_init(void);
-void sdram_init(void);
 
 /*
  * I/O Port configuration table
@@ -201,6 +200,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 int checkboard (void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       char buf[32];
 
        /* PCI slot in USER bits CSR[6:7] by convention. */
        uint pci_slot = get_pci_slot ();
@@ -223,8 +223,7 @@ int checkboard (void)
 
        printf("PCI1: %d bit, %s MHz, %s\n",
                (pci1_32) ? 32 : 64,
-               (pci1_speed == 33000000) ? "33" :
-               (pci1_speed == 66000000) ? "66" : "unknown",
+               strmhz(buf, pci1_speed),
                pci1_clk_sel ? "sync" : "async");
 
        if (pci_dual) {
@@ -242,48 +241,6 @@ int checkboard (void)
        return 0;
 }
 
-phys_size_t
-initdram(int board_type)
-{
-       long dram_size = 0;
-
-       puts("Initializing\n");
-
-#if defined(CONFIG_DDR_DLL)
-       {
-               /*
-                * Work around to stabilize DDR DLL MSYNC_IN.
-                * Errata DDR9 seems to have been fixed.
-                * This is now the workaround for Errata DDR11:
-                *    Override DLL = 1, Course Adj = 1, Tap Select = 0
-                */
-
-               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-               gur->ddrdllcr = 0x81000000;
-               asm("sync;isync;msync");
-               udelay(200);
-       }
-#endif
-       dram_size = fsl_ddr_sdram();
-       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-       dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-       /*
-        * Initialize and enable DDR ECC.
-        */
-       ddr_enable_ecc(dram_size);
-#endif
-       /*
-        * SDRAM Initialization
-        */
-       sdram_init();
-
-       puts("    DDR: ");
-       return dram_size;
-}
-
 /*
  * Initialize Local Bus
  */
@@ -334,8 +291,7 @@ local_bus_init(void)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
-void
-sdram_init(void)
+void lbc_sdram_init(void)
 {
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
@@ -345,9 +301,9 @@ sdram_init(void)
        uint cpu_board_rev;
        uint lsdmr_common;
 
-       puts("    SDRAM: ");
-
-       print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+       puts("LBC SDRAM: ");
+       print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+                  "\n       ");
 
        /*
         * Setup SDRAM Base and Option Registers