fsl-ddr: use the 1T timing as default configuration

[oweals/u-boot.git] / board / freescale / mpc8540ads / law.c

diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index ab6a6f25f5cd1ff2acc5ca55b31a2167f57b299c..f5644e154958c3df6852474ea4ff033ce537951b 100644 (file)
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-       SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+       SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-       SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
        /* This is not so much the SDRAM map as it is the whole localbus map. */
-       SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-       SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-       SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+       SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+       SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);