mx31pdk: Place machine ID into board config

[oweals/u-boot.git] / board / freescale / mpc837xemds / mpc837xemds.c

diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 85068923b7f313cfebfa8ad6eb3ac6dc1709b541..650a4fe483955740d5d67ee65479e0ac5d984324 100644 (file)
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
  * Dave Liu <daveliu@freescale.com>
  *
  * CREDITS: Kim Phillips contribute to LIBFDT code
@@ -11,19 +11,23 @@
  */
 
 #include <common.h>
+#include <hwconfig.h>
 #include <i2c.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <asm/fsl_enet.h>
 #include <spd_sdram.h>
 #include <tsec.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <fsl_mdio.h>
+#include <phy.h>
 #include "pci.h"
 #include "../common/pq-mds-pib.h"
 
 int board_early_init_f(void)
 {
-       struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
        u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
 
        /* Enable flash write */
@@ -31,18 +35,6 @@ int board_early_init_f(void)
        /* Clear all of the interrupt of BCSR */
        bcsr[0xe] = 0xff;
 
-#ifdef CONFIG_MMC
-       /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
-       bcsr[0xc] |= 0x4c;
-
-       /* Set proper bits in SICR to allow SD signals through */
-       clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
-
-       clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI),
-                       (SICRH_GPIO2_E_SD | SICRH_SPI_SD));
-
-#endif
-
 #ifdef CONFIG_FSL_SERDES
        immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
        u32 spridr = in_be32(&immr->sysconf.spridr);
@@ -72,9 +64,31 @@ int board_early_init_f(void)
        return 0;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+       struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+       u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+       if (!hwconfig("esdhc"))
+               return 0;
+
+       /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+       bcsr[0xc] |= 0x4c;
+
+       /* Set proper bits in SICR to allow SD signals through */
+       clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+       clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
+                       SICRH_GPIO2_E_SD | SICRH_SPI_SD);
+
+       return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
 int board_eth_init(bd_t *bd)
 {
+       struct fsl_pq_mdio_info mdio_info;
        struct tsec_info_struct tsec_info[2];
        struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
        u32 rcwh = in_be32(&im->reset.rcwh);
@@ -120,13 +134,17 @@ int board_eth_init(bd_t *bd)
        }
        num++;
 #endif
+
+       mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+       mdio_info.name = DEFAULT_MII_NAME;
+       fsl_pq_mdio_init(bd, &mdio_info);
+
        return tsec_eth_init(bd, tsec_info, num);
 }
 
 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
                            int phy_addr)
 {
-       const char *phy_type = "sgmii";
        const u32 *ph;
        int off;
        int err;
@@ -138,8 +156,8 @@ static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
                return;
        }
 
-       err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
-                         strlen(phy_type) + 1);
+       err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
+
        if (err) {
                printf("WARNING: could not set phy-connection-type for %s: "
                        "%s.\n", alias, fdt_strerror(err));
@@ -282,10 +300,9 @@ int board_pci_host_broken(void)
 {
        struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
        const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
-       const char *pci_ea = getenv("pci_external_arbiter");
 
        /* It's always OK in case of external arbiter. */
-       if (pci_ea && !strcmp(pci_ea, "yes"))
+       if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
                return 0;
 
        if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
@@ -322,6 +339,7 @@ void ft_board_setup(void *blob, bd_t *bd)
        ft_cpu_setup(blob, bd);
        ft_tsec_fixup(blob, bd);
        fdt_fixup_dr_usb(blob, bd);
+       fdt_fixup_esdhc(blob, bd);
 #ifdef CONFIG_PCI
        ft_pci_setup(blob, bd);
        if (board_pci_host_broken())