#endif
#include <spd_sdram.h>
#include <asm/mmu.h>
+#include <asm/io.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
+#include <hwconfig.h>
+#include <fdt_support.h>
#if defined(CONFIG_PQ_MDS_PIB)
#include "../common/pq-mds-pib.h"
#endif
+#include "../../../drivers/qe/uec.h"
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GETH1 */
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
-int board_early_init_f(void)
+/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
+static int board_handle_erratum2(void)
{
+ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+ return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
+ REVID_MINOR(immr->sysconf.spridr) == 1;
+}
+
+int board_early_init_f(void)
+{
const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
/* Enable flash write */
bcsr[0xa] &= ~0x04;
/* Enable second UART */
bcsr[0x9] &= ~0x01;
+ if (board_handle_erratum2()) {
+ void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
+
+ /*
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits_be32(immap, 0x0c003000);
+
+ /*
+ * IMMR + 0x14AC[20:27] = 10101010
+ * (data delay for both UCC's)
+ */
+ clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
+ }
return 0;
}
return 0;
}
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#ifdef CONFIG_UEC_ETH
+static uec_info_t uec_info[] = {
+#ifdef CONFIG_UEC_ETH1
+ STD_UEC_INFO(1),
+#endif
+#ifdef CONFIG_UEC_ETH2
+ STD_UEC_INFO(2),
+#endif
+};
+
+int board_eth_init(bd_t *bd)
+{
+ if (board_handle_erratum2()) {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uec_info); i++)
+ uec_info[i].enet_interface_type = RGMII_RXID;
+ uec_info[i].speed = 1000;
+ }
+ return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
+}
+#endif /* CONFIG_UEC_ETH */
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
-void sdram_init(void);
+static int sdram_init(unsigned int base);
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
+ u32 lbc_sdram_size;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
msize = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize DDR ECC byte
*/
/*
* Initialize SDRAM if it is on local bus.
*/
- sdram_init();
+ lbc_sdram_size = sdram_init(msize * 1024 * 1024);
+ if (!msize)
+ msize = lbc_sdram_size;
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
/*
* if MPC8360EMDS is soldered with SDRAM
*/
-#if defined(CONFIG_SYS_BR2_PRELIM) \
- && defined(CONFIG_SYS_OR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+#ifdef CONFIG_SYS_LB_SDRAM
/*
* Initialize SDRAM memory on the Local Bus.
*/
-void sdram_init(void)
+static int sdram_init(unsigned int base)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile lbus83xx_t *lbc = &immap->lbus;
- uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE;
+ volatile fsl_lbus_t *lbc = &immap->lbus;
+ const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
+ int rem = base % sdram_size;
+ uint *sdram_addr;
+
+ /* window base address should be aligned to the window size */
+ if (rem)
+ base = base - rem + sdram_size;
+ sdram_addr = (uint *)base;
/*
- * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ * Setup SDRAM Base and Option Registers
*/
+ immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
+ immap->lbus.bank[2].or = CONFIG_SYS_OR2;
+ immap->sysconf.lblaw[2].bar = base;
+ immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
+
/*setup mtrpt, lsrt and lbcr for LB bus */
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
+
+ /*
+ * In non-aligned case we don't [normally] use that memory because
+ * there is a hole.
+ */
+ if (rem)
+ return 0;
+ return CONFIG_SYS_LBC_SDRAM_SIZE;
}
#else
-void sdram_init(void)
-{
-}
+static int sdram_init(unsigned int base) { return 0; }
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
+ return;
+ do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+ ft_board_fixup_qe_usb(blob, bd);
/*
* mpc8360ea pb mds errata 2: RGMII timing
* if on mpc8360ea rev. 2.1,
* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
*/
- if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
- (REVID_MINOR(immr->sysconf.spridr) == 1)) {
+ if (board_handle_erratum2()) {
int nodeoffset;
const char *prop;
int path;
projects / oweals / u-boot.git / blobdiff