* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/mtd/mtd.h>
#define SET_CLE 0x10
-#define CLR_CLE ~SET_CLE
#define SET_ALE 0x08
-#define CLR_ALE ~SET_ALE
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- u32 nand_baseaddr = (u32) this->IO_ADDR_W;
-
- switch (cmd) {
- case NAND_CTL_SETNCE:
- case NAND_CTL_CLRNCE:
- break;
- case NAND_CTL_SETCLE:
- nand_baseaddr |= SET_CLE;
- break;
- case NAND_CTL_CLRCLE:
- nand_baseaddr &= CLR_CLE;
- break;
- case NAND_CTL_SETALE:
- nand_baseaddr |= SET_ALE;
- break;
- case NAND_CTL_CLRALE:
- nand_baseaddr |= CLR_ALE;
- break;
- case NAND_CTL_SETWP:
- fbcs->csmr2 |= FBCS_CSMR_WP;
- break;
- case NAND_CTL_CLRWP:
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
- break;
- }
- this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
-}
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
-static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
- struct nand_chip *this = mtdinfo->priv;
- *((volatile u8 *)(this->IO_ADDR_W)) = byte;
-}
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
-static u8 nand_read_byte(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtdinfo->priv;
- return (u8) (*((volatile u8 *)this->IO_ADDR_R));
-}
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
-static int nand_dev_ready(struct mtd_info *mtdinfo)
-{
- return 1;
+ if (ctrl & NAND_NCE)
+ *nCE &= 0xFFFB;
+ else
+ *nCE |= 0x0004;
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= SET_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= SET_ALE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
-
- /* set up pin configuration */
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
-
- nand->chip_delay = 50;
- nand->eccmode = NAND_ECC_SOFT;
- nand->hwcontrol = nand_hwcontrol;
- nand->read_byte = nand_read_byte;
- nand->write_byte = nand_write_byte;
- nand->dev_ready = nand_dev_ready;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
+
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
+
+ nand->chip_delay = 60;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
return 0;
}