imx8mm_evk: Include sys_proto.h header

[oweals/u-boot.git] / board / freescale / ls2080ardb / eth_ls2080rdb.c

diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 45f1d60322342e283264084c0a6702984c2fc19e..62c7a7a315502c4328a88a58a63e8298cd2d3af3 100644 (file)
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -50,21 +50,21 @@ int board_eth_init(bd_t *bis)
 
        switch (srds_s1) {
        case 0x2A:
-               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
-               wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
 
                break;
        case 0x4B:
-               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
-               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
-               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
-               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+               wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
 
                break;
        default: