treewide: fix "followings" to "following"

[oweals/u-boot.git] / board / freescale / ls2080aqds / README

diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 375e97c9b03894b7ef26e96fb8eef57a10bb3f3a..f28875099360c3115730b565dc7decd6b180e94f 100644 (file)
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
@@ -103,7 +64,7 @@ Memory map from core's view
 0x05_1000_0000 .. 0x05_FFFF_FFFF       IFC region #2
 0x80_8000_0000 .. 0xFF_FFFF_FFFF       DDR region #2
 
-Other addresses are either reserved, or not used directly by u-boot.
+Other addresses are either reserved, or not used directly by U-Boot.
 This list should be updated when more addresses are used.
 
 IFC region map from core's view
@@ -151,7 +112,7 @@ X-QSGMII-16PORT riser card
 ----------------------------
 The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
 interfaces implemented in PCIe form factor board.
-It supports followings
+It supports following:
  - Card can operate with up to 4 QSGMII lane simultaneously
  - Card can operate with up to 8 SGMII lane simultaneously