Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq
[oweals/u-boot.git] / board / freescale / ls1088a / ddr.c
index 0ecfd653b4513e161eef00e254ef3197fa2a65f1..78d573a8455620c05daf4a1a41fc0f59f6deddde 100644 (file)
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
+{
+       int vdd;
+
+       vdd = get_core_volt_from_fuse();
+       /* Nothing to do for silicons doesn't support VID */
+       if (vdd < 0)
+               return;
+
+       if (vdd == 900) {
+               popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
+               debug("VID: configure DDR to support 900 mV\n");
+       }
+}
+#endif
+
 void fsl_ddr_board_options(memctl_options_t *popts,
                           dimm_params_t *pdimm,
                           unsigned int ctrl_num)
@@ -87,6 +103,10 @@ found:
        popts->addr_hash = 1;
 
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+       fsl_ddr_setup_0v9_volt(popts);
+#endif
+
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
                          DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
 }
@@ -96,7 +116,10 @@ int fsl_initdram(void)
 {
        puts("Initializing DDR....using SPD\n");
 
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+       gd->ram_size = fsl_ddr_sdram_size();
+#else
        gd->ram_size = fsl_ddr_sdram();
-
+#endif
        return 0;
 }