fsl: layerscape: guard *env_sf_get_env_addr() on CONFIG_ENV_IS_IN_SPI_FLASH

[oweals/u-boot.git] / board / freescale / ls1046aqds / ls1046aqds.c

diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 552365b9d88854afd9d529e21739a8d828352675..aac5d9aa848fe31e72f73dc8b63b0c9df8795e5c 100644 (file)
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,17 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <ahci.h>
 #include <hwconfig.h>
 #include <mmc.h>
@@ -20,6 +24,7 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <fsl_sec.h>
 #include <spl.h>
 
 #include "../common/vid.h"
@@ -28,12 +33,140 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_TFABOOT
+struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+       {
+               "nor0",
+               CONFIG_SYS_NOR0_CSPR,
+               CONFIG_SYS_NOR0_CSPR_EXT,
+               CONFIG_SYS_NOR_AMASK,
+               CONFIG_SYS_NOR_CSOR,
+               {
+                       CONFIG_SYS_NOR_FTIM0,
+                       CONFIG_SYS_NOR_FTIM1,
+                       CONFIG_SYS_NOR_FTIM2,
+                       CONFIG_SYS_NOR_FTIM3
+               },
+
+       },
+       {
+               "nor1",
+               CONFIG_SYS_NOR1_CSPR,
+               CONFIG_SYS_NOR1_CSPR_EXT,
+               CONFIG_SYS_NOR_AMASK,
+               CONFIG_SYS_NOR_CSOR,
+               {
+                       CONFIG_SYS_NOR_FTIM0,
+                       CONFIG_SYS_NOR_FTIM1,
+                       CONFIG_SYS_NOR_FTIM2,
+                       CONFIG_SYS_NOR_FTIM3
+               },
+       },
+       {
+               "nand",
+               CONFIG_SYS_NAND_CSPR,
+               CONFIG_SYS_NAND_CSPR_EXT,
+               CONFIG_SYS_NAND_AMASK,
+               CONFIG_SYS_NAND_CSOR,
+               {
+                       CONFIG_SYS_NAND_FTIM0,
+                       CONFIG_SYS_NAND_FTIM1,
+                       CONFIG_SYS_NAND_FTIM2,
+                       CONFIG_SYS_NAND_FTIM3
+               },
+       },
+       {
+               "fpga",
+               CONFIG_SYS_FPGA_CSPR,
+               CONFIG_SYS_FPGA_CSPR_EXT,
+               CONFIG_SYS_FPGA_AMASK,
+               CONFIG_SYS_FPGA_CSOR,
+               {
+                       CONFIG_SYS_FPGA_FTIM0,
+                       CONFIG_SYS_FPGA_FTIM1,
+                       CONFIG_SYS_FPGA_FTIM2,
+                       CONFIG_SYS_FPGA_FTIM3
+               },
+       }
+};
+
+struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+       {
+               "nand",
+               CONFIG_SYS_NAND_CSPR,
+               CONFIG_SYS_NAND_CSPR_EXT,
+               CONFIG_SYS_NAND_AMASK,
+               CONFIG_SYS_NAND_CSOR,
+               {
+                       CONFIG_SYS_NAND_FTIM0,
+                       CONFIG_SYS_NAND_FTIM1,
+                       CONFIG_SYS_NAND_FTIM2,
+                       CONFIG_SYS_NAND_FTIM3
+               },
+       },
+       {
+               "nor0",
+               CONFIG_SYS_NOR0_CSPR,
+               CONFIG_SYS_NOR0_CSPR_EXT,
+               CONFIG_SYS_NOR_AMASK,
+               CONFIG_SYS_NOR_CSOR,
+               {
+                       CONFIG_SYS_NOR_FTIM0,
+                       CONFIG_SYS_NOR_FTIM1,
+                       CONFIG_SYS_NOR_FTIM2,
+                       CONFIG_SYS_NOR_FTIM3
+               },
+       },
+       {
+               "nor1",
+               CONFIG_SYS_NOR1_CSPR,
+               CONFIG_SYS_NOR1_CSPR_EXT,
+               CONFIG_SYS_NOR_AMASK,
+               CONFIG_SYS_NOR_CSOR,
+               {
+                       CONFIG_SYS_NOR_FTIM0,
+                       CONFIG_SYS_NOR_FTIM1,
+                       CONFIG_SYS_NOR_FTIM2,
+                       CONFIG_SYS_NOR_FTIM3
+               },
+       },
+       {
+               "fpga",
+               CONFIG_SYS_FPGA_CSPR,
+               CONFIG_SYS_FPGA_CSPR_EXT,
+               CONFIG_SYS_FPGA_AMASK,
+               CONFIG_SYS_FPGA_CSOR,
+               {
+                       CONFIG_SYS_FPGA_FTIM0,
+                       CONFIG_SYS_FPGA_FTIM1,
+                       CONFIG_SYS_FPGA_FTIM2,
+                       CONFIG_SYS_FPGA_FTIM3
+               },
+       }
+};
+
+void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+       enum boot_src src = get_boot_src();
+
+       if (src == BOOT_SOURCE_IFC_NAND)
+               regs_info->regs = ifc_cfg_nand_boot;
+       else
+               regs_info->regs = ifc_cfg_nor_boot;
+       regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+#endif
+
 enum {
        MUX_TYPE_GPIO,
 };
 
 int checkboard(void)
 {
+#ifdef CONFIG_TFABOOT
+       enum boot_src src = get_boot_src();
+#endif
        char buf[64];
 #ifndef CONFIG_SD_BOOT
        u8 sw;
@@ -41,6 +174,12 @@ int checkboard(void)
 
        puts("Board: LS1046AQDS, boot from ");
 
+#ifdef CONFIG_TFABOOT
+       if (src == BOOT_SOURCE_SD_MMC)
+               puts("SD\n");
+       else {
+#endif
+
 #ifdef CONFIG_SD_BOOT
        puts("SD\n");
 #else
@@ -59,6 +198,9 @@ int checkboard(void)
                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
 
+#ifdef CONFIG_TFABOOT
+       }
+#endif
        printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
               QIXIS_READ(id), QIXIS_READ(arch));
 
@@ -148,7 +290,12 @@ int dram_init(void)
         * before accessing DDR SPD.
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       gd->ram_size = initdram(0);
+       fsl_initdram();
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+       defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }
@@ -253,13 +400,31 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-       enable_layerscape_ns_access();
-#endif
-
        if (adjust_vdd(0))
                printf("Warning: Adjusting core voltage failed.\n");
 
+#ifdef CONFIG_FSL_LS_PPA
+       ppa_init();
+#endif
+
+#ifdef CONFIG_NXP_ESBC
+       /*
+        * In case of Secure Boot, the IBR configures the SMMU
+        * to allow only Secure transactions.
+        * SMMU must be reset in bypass mode.
+        * Set the ClientPD bit and Clear the USFCFG Bit
+        */
+       u32 val;
+       val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_SCR0, val);
+       val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+       sec_init();
+#endif
+
        return 0;
 }
 
@@ -284,6 +449,8 @@ int ft_board_setup(void *blob, bd_t *bd)
        fdt_fixup_board_enet(blob);
 #endif
 
+       fdt_fixup_icid(blob);
+
        reg = QIXIS_READ(brdcfg[0]);
        reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 
@@ -314,3 +481,10 @@ u16 flash_read16(void *addr)
 
        return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
+
+#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+void *env_sf_get_env_addr(void)
+{
+       return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
+}
+#endif