Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / board / freescale / ls1021atwr / ls1021atwr.c

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 616e0bfd39c486996a860348122b565998c2318d..d96fd774d36b3d7e5c8950fa298e053f1c8780df 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -10,7 +10,6 @@
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_sata.h>
@@ -28,7 +27,7 @@
 #include <spl.h>
 #include "../common/sleep.h"
 #ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
 #endif
 #include <fsl_validate.h>
 
@@ -143,7 +142,7 @@ int checkboard(void)
 void ddrmc_init(void)
 {
        struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
-       u32 temp_sdram_cfg;
+       u32 temp_sdram_cfg, tmp;
 
        out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 
@@ -190,6 +189,11 @@ void ddrmc_init(void)
        out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 
        out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+       /* DDR erratum A-009942 */
+       tmp = in_be32(&ddr->debug[28]);
+       out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
        udelay(1);
 
 #ifdef CONFIG_DEEP_SLEEP
@@ -448,43 +452,6 @@ void board_init_f(ulong dummy)
 }
 #endif
 
-
-struct liodn_id_table sec_liodn_tbl[] = {
-       SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
-       SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
-       SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
-       SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
-       SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
-       SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
-       SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
-       SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
-       SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
-};
-
-struct smmu_stream_id dev_stream_id[] = {
-       { 0x100, 0x01, "ETSEC MAC1" },
-       { 0x104, 0x02, "ETSEC MAC2" },
-       { 0x108, 0x03, "ETSEC MAC3" },
-       { 0x10c, 0x04, "PEX1" },
-       { 0x110, 0x05, "PEX2" },
-       { 0x114, 0x06, "qDMA" },
-       { 0x118, 0x07, "SATA" },
-       { 0x11c, 0x08, "USB3" },
-       { 0x120, 0x09, "QE" },
-       { 0x124, 0x0a, "eSDHC" },
-       { 0x128, 0x0b, "eMA" },
-       { 0x14c, 0x0c, "2D-ACE" },
-       { 0x150, 0x0d, "USB2" },
-       { 0x18c, 0x0e, "DEBUG" },
-};
-
 #ifdef CONFIG_DEEP_SLEEP
 /* program the regulator (MC34VR500) to support deep sleep */
 void ls1twr_program_regulator(void)
@@ -518,6 +485,10 @@ void ls1twr_program_regulator(void)
 
 int board_init(void)
 {
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+       erratum_a010315();
+#endif
+
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        fsl_serdes_init();
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
@@ -525,14 +496,7 @@ int board_init(void)
 #endif
 #endif
 
-       ls1021x_config_caam_stream_id(sec_liodn_tbl,
-                                     ARRAY_SIZE(sec_liodn_tbl));
-       ls102xa_config_smmu_stream_id(dev_stream_id,
-                                     ARRAY_SIZE(dev_stream_id));
-
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-       enable_layerscape_ns_access();
-#endif
+       ls102xa_smmu_stream_id_init();
 
 #ifdef CONFIG_U_QE
        u_qe_init();
@@ -544,6 +508,13 @@ int board_init(void)
        return 0;
 }
 
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+       ls102xa_smmu_stream_id_init();
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {