#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/pcie_layerscape.h>
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_sata.h>
+#include <hwconfig.h>
#include <mmc.h>
+#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
+#include <fsl_immap.h>
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
+#include <fsl_devdis.h>
#include <spl.h>
+#include "../common/sleep.h"
#ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
#endif
+#include <fsl_validate.h>
DECLARE_GLOBAL_DATA_PTR;
#define KEEP_STATUS 0x0
#define NEED_RESET 0x1
+#define SOFT_MUX_ON_I2C3_IFC 0x2
+#define SOFT_MUX_ON_CAN3_USB2 0x8
+#define SOFT_MUX_ON_QE_LCD 0x10
+
+#define PIN_I2C3_IFC_MUX_I2C3 0x0
+#define PIN_I2C3_IFC_MUX_IFC 0x1
+#define PIN_CAN3_USB2_MUX_USB2 0x0
+#define PIN_CAN3_USB2_MUX_CAN3 0x1
+#define PIN_QE_LCD_MUX_LCD 0x0
+#define PIN_QE_LCD_MUX_QE 0x1
+
struct cpld_data {
u8 cpld_ver; /* cpld revision */
u8 cpld_ver_sub; /* cpld sub revision */
u8 rev2; /* Reserved */
};
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
in_8(&cpld_data->serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
cpld_show();
+#endif
return 0;
}
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+ u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
- out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ out_be32(&ddr->sdram_cfg_2,
+ DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
+ out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_ext_addr, (1 << 31));
+
+ /* DRAM VRef will not be trained */
+ out_be32(&ddr->ddr_cdr2,
+ DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
+ } else
+#endif
+ {
+ out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+ out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+ }
out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
- out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+ /* DDR erratum A-009942 */
+ tmp = in_be32(&ddr->debug[28]);
+ out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
udelay(1);
- out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* enter self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
+ } else
+#endif
+ temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+
+#ifdef CONFIG_DEEP_SLEEP
+ if (is_warm_boot()) {
+ /* exit self-refresh */
+ temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
+ temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
+ out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
+ }
+#endif
}
int dram_init(void)
#endif
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return 0;
}
}
#endif
-#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
+#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
+#endif
return pci_eth_init(bis);
}
-#endif
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return 0;
}
+#endif
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+int config_board_mux(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ int conflict_flag;
+
+ conflict_flag = 0;
+ if (hwconfig("i2c3")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+ cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
+ }
+
+ if (hwconfig("ifc")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
+ cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("usb2")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+ cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
+ }
+
+ if (hwconfig("can3")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
+ cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("lcd")) {
+ conflict_flag++;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+ cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
+ }
+
+ if (hwconfig("qe")) {
+ conflict_flag++;
+ /* some signals can not enable simultaneous*/
+ if (conflict_flag > 1)
+ goto conflict;
+ cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
+ cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
+ }
+
+ return 0;
+
+conflict:
+ printf("WARNING: pin conflict! MUX setting may failed!\n");
+ return 0;
+}
+#endif
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
- out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ /* clear BD & FR bits for BE BD's and frame data */
+ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
init_early_memctl_regs();
#endif
-#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+ arch_soc_init();
+
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot()) {
+ timer_init();
+ dram_init();
+ }
#endif
return 0;
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- /* Set global data pointer */
- gd = &gdata;
+ void (*second_uboot)(void);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
dram_init();
+ /* Allow OCRAM access permission as R/W */
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+ enable_layerscape_ns_access();
+#endif
+
+ /*
+ * if it is woken up from deep sleep, then jump to second
+ * stage uboot and continue executing without recopying
+ * it from SD since it has already been reserved in memeory
+ * in last boot.
+ */
+ if (is_warm_boot()) {
+ second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
+ second_uboot();
+ }
+
board_init_r(NULL, 0);
}
#endif
-int board_init(void)
+#ifdef CONFIG_DEEP_SLEEP
+/* program the regulator (MC34VR500) to support deep sleep */
+void ls1twr_program_regulator(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ unsigned int i2c_bus;
+ u8 i2c_device_id;
+
+#define LS1TWR_I2C_BUS_MC34VR500 1
+#define MC34VR500_ADDR 0x8
+#define MC34VR500_DEVICEID 0x4
+#define MC34VR500_DEVICEID_MASK 0x0f
+
+ i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
+ i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
+ MC34VR500_DEVICEID_MASK;
+ if (i2c_device_id != MC34VR500_DEVICEID) {
+ printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
+ return;
+ }
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
+ i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
+ i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
+ i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
+
+ i2c_set_bus_num(i2c_bus);
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_serdes_mux();
#endif
+#endif
+
+ ls102xa_smmu_stream_id_init();
#ifdef CONFIG_U_QE
u_qe_init();
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ ls1twr_program_regulator();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+ ls102xa_smmu_stream_id_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ ls1021a_sata_init();
+#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
+
return 0;
}
+#endif
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+ device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+#endif
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+ config_board_mux();
+#endif
+
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCIE_LAYERSCAPE
- ft_pcie_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
#endif
return 0;
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
" -change lane C & lane D to PCIeX2\n"
"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
);
+#endif