Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[oweals/u-boot.git] / board / freescale / ls1021aqds / ls1021aqds.c

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 20eade46514114ee6432f0bedf4e10af7c99b060..92f613ad2419304527a358288045e4784a107ae2 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -12,7 +12,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
-#include <asm/pcie_layerscape.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -138,6 +137,17 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
+unsigned int get_soc_major_rev(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       unsigned int svr, major;
+
+       svr = in_be32(&gur->svr);
+       major = SVR_MAJ(svr);
+
+       return major;
+}
+
 int select_i2c_ch_pca9547(u8 ch)
 {
        int ret;
@@ -181,6 +191,7 @@ int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
        out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -205,19 +216,22 @@ int board_early_init_f(void)
        out_le32(&cci->slave[4].snoop_ctrl,
                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
-       /*
-        * Set CCI-400 Slave interface S1, S2 Shareable Override Register
-        * All transactions are treated as non-shareable
-        */
-       out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
-       /* Workaround for the issue that DDR could not respond to
-        * barrier transaction which is generated by executing DSB/ISB
-        * instruction. Set CCI-400 control override register to
-        * terminate the barrier transaction. After DDR is initialized,
-        * allow barrier transaction to DDR again */
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+       major = get_soc_major_rev();
+       if (major == SOC_MAJOR_VER_1_0) {
+               /*
+                * Set CCI-400 Slave interface S1, S2 Shareable Override
+                * Register All transactions are treated as non-shareable
+                */
+               out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+               out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+               /* Workaround for the issue that DDR could not respond to
+                * barrier transaction which is generated by executing DSB/ISB
+                * instruction. Set CCI-400 control override register to
+                * terminate the barrier transaction. After DDR is initialized,
+                * allow barrier transaction to DDR again */
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+       }
 
 #if defined(CONFIG_DEEP_SLEEP)
        if (is_warm_boot())
@@ -231,6 +245,7 @@ int board_early_init_f(void)
 void board_init_f(ulong dummy)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       unsigned int major;
 
 #ifdef CONFIG_NAND_BOOT
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
@@ -267,7 +282,10 @@ void board_init_f(ulong dummy)
 #ifdef CONFIG_SPL_I2C_SUPPORT
        i2c_init_all();
 #endif
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+       major = get_soc_major_rev();
+       if (major == SOC_MAJOR_VER_1_0)
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 
        dram_init();
 
@@ -509,6 +527,25 @@ static struct csu_ns_dev ns_dev[] = {
 };
 #endif
 
+struct liodn_id_table sec_liodn_tbl[] = {
+       SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
+       SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
+       SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
+       SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
+       SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
+       SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
+       SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
+       SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
+       SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
+};
+
 struct smmu_stream_id dev_stream_id[] = {
        { 0x100, 0x01, "ETSEC MAC1" },
        { 0x104, 0x02, "ETSEC MAC2" },
@@ -529,10 +566,14 @@ struct smmu_stream_id dev_stream_id[] = {
 int board_init(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       unsigned int major;
 
-       /* Set CCI-400 control override register to
-        * enable barrier transaction */
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+       major = get_soc_major_rev();
+       if (major == SOC_MAJOR_VER_1_0) {
+               /* Set CCI-400 control override register to
+                * enable barrier transaction */
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+       }
 
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
@@ -541,6 +582,8 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
+       ls1021x_config_caam_stream_id(sec_liodn_tbl,
+                                     ARRAY_SIZE(sec_liodn_tbl));
        ls102xa_config_smmu_stream_id(dev_stream_id,
                                      ARRAY_SIZE(dev_stream_id));
 
@@ -559,10 +602,15 @@ int board_init(void)
 void board_sleep_prepare(void)
 {
        struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       unsigned int major;
+
+       major = get_soc_major_rev();
+       if (major == SOC_MAJOR_VER_1_0) {
+               /* Set CCI-400 control override register to
+                * enable barrier transaction */
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+       }
 
-       /* Set CCI-400 control override register to
-        * enable barrier transaction */
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
 #ifdef CONFIG_LS102XA_NS_ACCESS
        enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
@@ -574,8 +622,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCIE_LAYERSCAPE
-       ft_pcie_setup(blob, bd);
+#ifdef CONFIG_PCI
+       ft_pci_setup(blob, bd);
 #endif
 
        return 0;