// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
#include <i2c.h>
+#include <init.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <hwconfig.h>
#include <mmc.h>
#include <fsl_csu.h>
-#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
return 66666666;
}
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return ret;
+ }
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
+ *
+ * PCA9547(0x77) mount on I2C1 bus
*/
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return fsl_initdram();
}
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {CONFIG_SYS_FSL_ESDHC_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_CCI400_OFFSET);
- unsigned int major;
-
#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
i2c_init_all();
#endif
- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0)
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
-
timer_init();
dram_init();
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_CCI400_OFFSET);
- unsigned int major;
-
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
erratum_a009942_check_cpo();
#endif
- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
- /* Set CCI-400 control override register to
- * enable barrier transaction */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- }
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
- struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
- CONFIG_SYS_CCI400_OFFSET);
- unsigned int major;
-
- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
- /* Set CCI-400 control override register to
- * enable barrier transaction */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- }
-
-
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif