mpc83xx: Get rid of CONFIG_SYS_DDR_BASE

[oweals/u-boot.git] / board / freescale / bsc9132qds / ddr.c

diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index 05bea8ad5248a96404e1c3d6ec9a126e485053e2..191ef01d23e48923030bd6f543d68a37595e50e9 100644 (file)
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -1,20 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #ifndef CONFIG_SYS_DDR_RAW_TIMING
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
@@ -109,7 +106,7 @@ phys_size_t fixed_sdram(void)
                                        strmhz(buf, ddr_freq));
 
        ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+       fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
        if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
                                        LAW_TRGT_IF_DDR_1) < 0) {
@@ -136,20 +133,20 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 0,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1870,
-       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
-       .tAA_ps = 13125,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13125,
-       .tRRD_ps = 7500,
-       .tRP_ps = 13125,
-       .tRAS_ps = 37500,
-       .tRC_ps = 50625,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 7500,
-       .tRTP_ps = 7500,
+       .tckmin_x_ps = 1870,
+       .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
+       .taa_ps = 13125,
+       .twr_ps = 15000,
+       .trcd_ps = 13125,
+       .trrd_ps = 7500,
+       .trp_ps = 13125,
+       .tras_ps = 37500,
+       .trc_ps = 50625,
+       .trfc_ps = 160000,
+       .twtr_ps = 7500,
+       .trtp_ps = 7500,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 37500,
+       .tfaw_ps = 37500,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,