Merge tag 'efi-2020-07-rc2-4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / board / freescale / b4860qds / ddr.c

diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 31b186ea8ce9c51aaf35ed26dfc32d0a763ee764..de9f5f5f8bcb82071fa11534a09bb40be867e9f3 100644 (file)
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <common.h>
@@ -171,9 +170,12 @@ found:
        /* DHC_EN =1, ODT = 75 Ohm */
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
        phys_size_t dram_size;
 
@@ -186,7 +188,9 @@ phys_size_t initdram(int board_type)
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-       return dram_size;
+       gd->ram_size = dram_size;
+
+       return 0;
 }
 
 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
@@ -210,7 +214,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 
                debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
                      rank_density, ctlr_density);
-               for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+               for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
                        switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
                        case FSL_DDR_CACHE_LINE_INTERLEAVING:
                        case FSL_DDR_PAGE_INTERLEAVING:
@@ -234,7 +238,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
                 * Simple linear assignment if memory
                 * controllers are not interleaved.
                 */
-               for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+               for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
                        total_ctlr_mem = 0;
                        pinfo->common_timing_params[i].base_address =
                                                current_mem_base;