ppc4xx: Convert PPC4xx UIC defines from lower case to upper case

[oweals/u-boot.git] / board / esd / du440 / du440.c

diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 376de98354816832a1a8be78daba72a27d317bf2..056f455d687ba27a9aa34fe4470ffd999bc07f74 100644 (file)
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -87,37 +87,37 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 
        /*
         * UIC1:
         *  bit30: ext. Irq 1: PLD : int 32+30
         */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xfffffffd);
-       mtdcr(uic1tr, 0x00000000);
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xfffffffd);
+       mtdcr(UIC1TR, 0x00000000);
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*
         * UIC2
         *  bit3: ext. Irq 2: DCF77 : int 64+3
         */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 
        /* select Ethernet pins */
        mfsdr(SDR0_PFC1, sdr0_pfc1);