#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
+#include <pci.h>
-/* ------------------------------------------------------------------------- */
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
-
-
#include "../common/auto_update.h"
#ifdef CONFIG_CPCI405AB
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
/* Prototypes */
int cpci405_version(void);
int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
-
int board_early_init_f (void)
{
#ifndef CONFIG_CPCI405_VER2
#endif
#ifdef FPGA_DEBUG
- DECLARE_GLOBAL_DATA_PTR;
-
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
if (status != 0) {
/* booting FPGA failed */
#ifndef FPGA_DEBUG
- DECLARE_GLOBAL_DATA_PTR;
-
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
- mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+#else
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+#endif
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
-
/* ------------------------------------------------------------------------- */
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
else
- return -1; /* yes, board is cterm-m2 */
+ return -1; /* yes, board is cterm-m2 */
#endif
}
-
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- return -1; /* yes, board is cpci405 host */
+ return -1; /* yes, board is cpci405 host */
else
- return 0; /* no, board is cpci405 adapter */
+ return 0; /* no, board is cpci405 adapter */
}
-
int cpci405_version(void)
{
unsigned long cntrl0Reg;
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
- udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
/* CS2==0 && CS3==1 -> version 2 */
return 2;
case 0x00100000:
- /* CS2==1 && CS3==0 -> version 3 */
+ /* CS2==1 && CS3==0 -> version 3 or 6U board */
return 3;
case 0x00000000:
/* CS2==0 && CS3==0 -> version 4 */
}
}
-
int misc_init_f (void)
{
return 0; /* dummy implementation */
}
-
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
unsigned long cntrl0Reg;
/* adjust flash start and offset */
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
-
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
+#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
+#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
return (0);
}
-
/*
* Check Board Identity:
*/
int index;
int len;
#endif
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned short ver;
#endif
if (ctermm2()) {
- unsigned char str[4];
+ char str[4];
/*
* Read board-id and save in env-variable
}
#ifndef CONFIG_CPCI405_VER2
- puts ("\nFPGA: ");
+ puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
#endif
putc ('\n');
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
return 0;
}
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
unsigned long val;
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
- return (0);
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
}
/* ------------------------------------------------------------------------- */
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = 0xff;
+
+ /*
+ * Write pci interrupt line register (cpci405 specific)
+ */
+ switch (PCI_DEV(dev) & 0x03) {
+ case 0:
+ int_line = 27 + 2;
+ break;
+ case 1:
+ int_line = 27 + 3;
+ break;
+ case 2:
+ int_line = 27 + 0;
+ break;
+ case 3:
+ int_line = 27 + 1;
+ break;
+ }
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = cpci405_pci_fixup_irq;
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
#ifdef CONFIG_CPCI405AB
-#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|= CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
&= ~CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
& CFG_FPGA_MODE_1WIRE)
/*
return result;
}
-
/*
* Send 1 a 1-wire write bit.
* Provide 10us recovery time.
}
}
-
/*
* Read a bit from the 1-wire bus and return it.
* Provide 10us recovery time.
return result;
}
-
void OWWriteByte(int data)
{
int loop;
}
}
-
int OWReadByte(void)
{
int loop, result = 0;
return result;
}
-
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned short val;
int result;
int i;
unsigned char ow_id[6];
- unsigned char str[32];
+ char str[32];
unsigned char ow_crc;
/*
NULL
);
-
#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
*/
int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- DECLARE_GLOBAL_DATA_PTR;
-
bd_t *bd = gd->bd;
char *buf;
ulong crc;
IPaddr_t ipaddr;
buf = malloc(CFG_ENV_SIZE_2);
- if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError reading backplane EEPROM!\n");
} else {
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
if (crc != *(ulong *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
return -1;
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *buf;
- unsigned char str[32];
+ char str[32];
ulong crc;
if (argc < 2) {
memset(buf, 0, CFG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
- crc = crc32(0, buf+4, CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
*(ulong *)buf = crc;
- if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
puts("\nError writing backplane EEPROM!\n");
}
projects / oweals / u-boot.git / blobdiff