Merge branch 'master' of git://www.denx.de/git/u-boot-avr32

[oweals/u-boot.git] / board / esd / cpci405 / cpci405.c

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 58f792e2e4a1858db33659d1f3a5632e3cdd79ab..b856705ff98a698b109265120f7a8f9ef465aec0 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -31,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);      /*cmd_boot.c*/
 #if 0
 #define FPGA_DEBUG
 #endif
@@ -109,10 +109,10 @@ int board_early_init_f (void)
        /*
         * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
         */
-       out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
-       out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+       out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+       out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
        out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
-       out32(GPIO0_OR, 0);                  /* pull prg low            */
+       out32(GPIO0_OR, 0);                  /* pull prg low            */
 
        /*
         * Boot onboard FPGA
@@ -174,21 +174,21 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(uicer, 0x00000000);       /* disable all ints */
+       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 #ifdef CONFIG_CPCI405_6U
        if (cpci405_version() == 3) {
-               mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
+               mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
        } else {
-               mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+               mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
        }
 #else
-       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
 #endif
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 
        return 0;
 }
@@ -198,22 +198,22 @@ int board_early_init_f (void)
 int ctermm2(void)
 {
 #ifdef CONFIG_CPCI405_VER2
-       return 0;                       /* no, board is cpci405 */
+       return 0;                       /* no, board is cpci405 */
 #else
        if ((*(unsigned char *)0xf0000400 == 0x00) &&
            (*(unsigned char *)0xf0000401 == 0x01))
-               return 0;               /* no, board is cpci405 */
+               return 0;               /* no, board is cpci405 */
        else
-               return -1;              /* yes, board is cterm-m2 */
+               return -1;              /* yes, board is cterm-m2 */
 #endif
 }
 
 int cpci405_host(void)
 {
        if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
-               return -1;              /* yes, board is cpci405 host */
+               return -1;              /* yes, board is cpci405 host */
        else
-               return 0;               /* no, board is cpci405 adapter */
+               return 0;               /* no, board is cpci405 adapter */
 }
 
 int cpci405_version(void)
@@ -228,8 +228,8 @@ int cpci405_version(void)
        mtdcr(cntrl0, cntrl0Reg | 0x03000000);
        out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
-       udelay(1000);                   /* wait some time before reading input */
-       value = in_be32((void*)GPIO0_IR) & 0x00180000;       /* get config bits */
+       udelay(1000);                   /* wait some time before reading input */
+       value = in_be32((void*)GPIO0_IR) & 0x00180000;       /* get config bits */
 
        /*
         * Restore GPIO settings
@@ -478,7 +478,7 @@ int checkboard (void)
        }
 
 #ifndef CONFIG_CPCI405_VER2
-       puts ("\nFPGA:  ");
+       puts ("\nFPGA:  ");
 
        /* display infos on fpgaimage */
        index = 15;
@@ -495,7 +495,7 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
        unsigned long val;
 
@@ -574,11 +574,11 @@ int pci_pre_init(struct pci_controller *hose)
 
 #ifdef CONFIG_CPCI405AB
 
-#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_CLEAR  (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
                          |= CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_SET    (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
                          &= ~CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+#define ONE_WIRE_GET    (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
                          & CFG_FPGA_MODE_1WIRE)
 
 /*