doc/README.scrapyard: update commit IDs

[oweals/u-boot.git] / board / emk / top5200 / top5200.c

diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
index 63a4ee4698bf5635439957dd2785f76d59c9748c..8eaf7cbde3071036a063f68758f2b508173b36ae 100644 (file)
--- a/board/emk/top5200/top5200.c
+++ b/board/emk/top5200/top5200.c
@@ -5,23 +5,7 @@
  * (C) Copyright 2003
  * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -32,10 +16,10 @@
  * initialize SDRAM/DDRAM controller.
  * TBD: get data from I2C EEPROM
  *****************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
        ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #if 0
        ulong   t;
        ulong   tap_del;
@@ -46,33 +30,33 @@ long int initdram (int board_type)
        #define SOFT_REF        4
 
        /* configure SDRAM start/end */
-       *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
+       *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;  /* disabled */
 
        /* setup config registers */
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
-       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
+       *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
 
        /* unlock mode register */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
        /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#ifdef CFG_DRAM_DDR
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CONFIG_SYS_DRAM_DDR
        /* set extended mode register */
-       *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
+       *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
 #endif
        /* set mode register */
-       *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
+       *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
        /* precharge all banks */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
        /* auto refresh */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
        /* set mode register */
-       *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
+       *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
        /* normal operation */
-       *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
+       *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
        /* write default TAP delay */
-       *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
+       *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
 
 #if 0
        for (tap_del = 0; tap_del < 32; tap_del++)
@@ -97,7 +81,7 @@ long int initdram (int board_type)
                }
        }
 #endif
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
        dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 
@@ -182,21 +166,27 @@ void pci_init_board(void)
 #endif
 
 /*****************************************************************************
- * provide the PCI Reset Function
+ * provide the IDE Reset Function
  *****************************************************************************/
-#ifdef CFG_CMD_IDE
-#define GPIO_PSC1_4    0x01000000ul
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+       debug ("init_ide_reset\n");
+
+       /* Configure PSC1_4 as GPIO output for ATA reset */
+       *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+       *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
 void ide_set_reset (int idereset)
 {
+       debug ("ide_reset(%d)\n", idereset);
+
        if (idereset) {
-               *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+               *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
        } else {
-               *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+               *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
        }
-
-       /* Configure PSC1_4 as GPIO output for ATA reset */
-       /* (it does not matter we do this every time) */
-       *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-       *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
 }
 #endif