*/
#include <config.h>
-#include <mpc75x.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
#include <mpc106.h>
#include <version.h>
lis r2, 0xfee0
ori r2, r2, 0xcfc
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
/*
* Switch to address map A if necessary.
*/
beq SD16MB2B
li r3, 0x0011 /* get number of internal banks */
- /* from spd for bank0/1 */
+ /* from spd for bank0/1 */
bl spdRead
cmpli 0, 0, r3, 0x02
* set the Memory Configuration Reg. 2
*/
li r3, 0x0111 /* get number of internal banks */
- /* from spd for bank2/3 */
+ /* from spd for bank2/3 */
bl spdRead
cmpli 0, 0, r3, 0x02
*/
S2D64MB4B:
lis r21, 0x8630 /* BSTOPRE = 0x80, REFREC = 6, */
- /* RDLAT = 3 */
+ /* RDLAT = 3 */
/*
* set the Memory Configuration Reg. 4
*/
lis r22, 0x2430 /* PRETOACT = 2, ACTOPRE = 4, */
- /* WCBUF = 1, RCBUF = 1 */
+ /* WCBUF = 1, RCBUF = 1 */
ori r22, r22, 0x2220 /* SDMODE = 0x022, ACTORW = 2 */
/*
bl spdRead
rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte */
- /* (128 MB max.) */
+ /* (128 MB max.) */
li r3, 0x0005 /* get number of banks from spd */
- /* for bank0/1 */
+ /* for bank0/1 */
bl spdRead
cmpi 0, 0, r3, 2 /* 2 banks ? */
bl spdRead
rlwinm r18, r3, 2, 24, 29 /* calculate size in MByte */
- /* (128 MB max.) */
+ /* (128 MB max.) */
li r3, 0x0105 /* get number of banks from */
- /* spd bank0/1 */
+ /* spd bank0/1 */
bl spdRead
cmpi 0, 0, r3, 2 /* 2 banks ? */
getSpdRowBank01:
li r3, 0x0003 /* get number of row bits from */
- /* spd from bank0/1 */
+ /* spd from bank0/1 */
bl spdRead
ori r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
cmpli 0, 0, r3, 0x0009 /* bank0 - 9 row bits */
getSpdRowBank23:
li r3, 0x0103 /* get number of row bits from */
- /* spd for bank2/3 */
+ /* spd for bank2/3 */
bl spdRead
ori r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
writeRowBits:
lis r21, 0x000a /* CPX = 1, RAS6P = 4 */
ori r21, r21, 0x2293 /* CAS5 = 2, CP4 = 1, */
- /* CAS3 = 2, RCD2 = 2, RP = 3 */
+ /* CAS3 = 2, RCD2 = 2, RP = 3 */
/*
* set the Memory Configuration Reg. 4
*/
lis r22, 0x0010 /* all SDRAM parameter 0, */
- /* WCBUF flow through, */
- /* RCBUF registered */
+ /* WCBUF flow through, */
+ /* RCBUF registered */
/*
* get the size of bank 0-3
*/
bl spdRead
li r16, 0 /* bank size is: */
- /* (8*2^row*2^column)/0x100000 MB */
+ /* (8*2^row*2^column)/0x100000 MB */
ori r16, r16, 0x8000
rlwnm r16, r16, r3, 0, 31
rlwnm r16, r16, r3, 0, 31
li r3, 0x0005 /* get number of banks from */
- /* spd for bank0/1 */
+ /* spd for bank0/1 */
bl spdRead
cmpi 0, 0, r3, 2 /* 2 banks ? */
bl spdRead
li r18, 0 /* bank size is: */
- /* (8*2^row*2^column)/0x100000 MB */
+ /* (8*2^row*2^column)/0x100000 MB */
ori r18, r18, 0x8000
rlwnm r18, r18, r3, 0, 31
rlwnm r18, r18, r3, 0, 31
li r3, 0x0105 /* get number of banks from */
- /* spd for bank2/3 */
+ /* spd for bank2/3 */
bl spdRead
cmpi 0, 0, r3, 2 /* 2 banks ? */
common3:
li r4, 0x1010 /* refesh cycle 1028 clocks */
- /* left shifted 2 */
+ /* left shifted 2 */
cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */
beq writeRefresh
li r4, 0x0808 /* refesh cycle 514 clocks */
- /* left shifted 2 */
+ /* left shifted 2 */
cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */
beq writeRefresh
li r4, 0x2020 /* refesh cycle 2056 clocks */
- /* left shifted 2 */
+ /* left shifted 2 */
cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */
beq writeRefresh
li r4, 0x4040 /* refesh cycle 4112 clocks */
- /* left shifted 2 */
+ /* left shifted 2 */
cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */
beq writeRefresh
li r4, 0
ori r4, r4, 0x8080 /* refesh cycle 8224 clocks */
- /* left shifted 2 */
+ /* left shifted 2 */
cmpli 0, 0, r3, 0x0005 /* 125 us ? */
beq writeRefresh
/*
* Get base addr of ISA I/O space
*/
- lis r6, CFG_ISA_IO@h
- ori r6, r6, CFG_ISA_IO@l
+ lis r6, CONFIG_SYS_ISA_IO@h
+ ori r6, r6, CONFIG_SYS_ISA_IO@l
/*
* Set offset to base address for config registers.
*/
-#if defined(CFG_NS87308_BADDR_0x)
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
addi r4, r0, 0x0279
-#elif defined(CFG_NS87308_BADDR_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
addi r4, r0, 0x015C
-#elif defined(CFG_NS87308_BADDR_11)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
addi r4, r0, 0x002E
#endif
add r6, r6, r4 /* add offset to base */
addi r5, r0, SIO_LUNENABLE
bl .sio_bw
- lis r8, CFG_ISA_IO@h
+ lis r8, CONFIG_SYS_ISA_IO@h
ori r8, r8, 0x0460
li r9, 0x03
stb r9, 0(r8) /* select PMC2 register */
/*
* Init COM1 for polled output
*/
- lis r8, CFG_ISA_IO@h
+ lis r8, CONFIG_SYS_ISA_IO@h
ori r8, r8, 0x03f8
li r9, 0x00
stb r9, 1(r8) /* int disabled */
eieio
li r9, 0x03
stb r9, 3(r8) /* 8 data bits, 1 stop bit, */
- /* no parity */
+ /* no parity */
eieio
li r9, 0x0b
stb r9, 4(r8) /* enable the receiver and transmitter */
beq waitEmpty
li r9, 0x47
stb r9, 3(r8) /* send break, 8 data bits, */
- /* 2 stop bits, no parity */
+ /* 2 stop bits, no parity */
eieio
lis r0, 0x0001
beq waitEmpty1
li r9, 0x07
stb r9, 3(r8) /* 8 data bits, 2 stop bits, */
- /* no parity */
+ /* no parity */
eieio
/*
/*
* Get base addr of ISA I/O space
*/
- lis r3, CFG_ISA_IO@h
- ori r3, r3, CFG_ISA_IO@l
+ lis r3, CONFIG_SYS_ISA_IO@h
+ ori r3, r3, CONFIG_SYS_ISA_IO@l
addi r3, r3, 0x015C /* adjust to superI/O 87308 base */
or r6, r3, r3 /* make a copy */
*/
.globl Printf
Printf:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
WaitChr:
OutHex:
li r9, 28 /* shift reg for 8 digits */
OHstart:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutDig:
lbz r0, 5(r10) /* read link status */
mullw r10, r0, r6
subf r7, r10, r3
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
or. r7, r7, r7
*/
.globl OutChr
OutChr:
- lis r10, CFG_ISA_IO@h /* COM1 port */
+ lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutChr1:
spdRead:
mfspr r26, 8 /* save link register */
- lis r30, CFG_ISA_IO@h
+ lis r30, CONFIG_SYS_ISA_IO@h
ori r30, r30, 0x220 /* GPIO Port 1 */
li r7, 0x00
li r8, 0x100
Mmbyte:
.ascii " MB .......... \000"
.align 4
-
-
-
-
-
-
-
-
-
-
-
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projects / oweals / u-boot.git / blobdiff