Merge git://git.denx.de/u-boot-usb

[oweals/u-boot.git] / board / denx / mcvevk / qts / sdram_config.h

diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
index cf9d1d3affd9bafc2774b5d2d7792d53a81d04e2..30c4d7d02a4e5e6855ffc7fe857a7c663906d092 100644 (file)
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ b/board/denx/mcvevk/qts/sdram_config.h
@@ -34,19 +34,19 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        117
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1300
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        12
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 17
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
@@ -132,7 +132,7 @@
 #define ENABLE_SUPER_QUICK_CALIBRATION 0
 #define IO_DELAY_PER_DCHAIN_TAP        25
 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#define IO_DELAY_PER_OPA_TAP   375
+#define IO_DELAY_PER_OPA_TAP   312
 #define IO_DLL_CHAIN_LENGTH    8
 #define IO_DQDQS_OUT_PHASE_MAX 0
 #define IO_DQS_EN_DELAY_MAX    31
@@ -147,7 +147,7 @@
 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
 #define MAX_LATENCY_COUNT_WIDTH        5
 #define READ_VALID_FIFO_SIZE   16
-#define REG_FILE_INIT_SEQ_SIGNATURE    0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE    0x55550496
 #define RW_MGR_MEM_ADDRESS_MIRRORING   0
 #define RW_MGR_MEM_DATA_MASK_WIDTH     4
 #define RW_MGR_MEM_DATA_WIDTH  32
@@ -160,10 +160,10 @@
 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS        1
 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH        4
-#define TINIT_CNTR0_VAL        82
+#define TINIT_CNTR0_VAL        99
 #define TINIT_CNTR1_VAL        32
 #define TINIT_CNTR2_VAL        32
-#define TRESET_CNTR0_VAL       82
+#define TRESET_CNTR0_VAL       99
 #define TRESET_CNTR1_VAL       99
 #define TRESET_CNTR2_VAL       10
 
@@ -171,14 +171,14 @@
 const u32 ac_rom_init[] = {
        0x20700000,
        0x20780000,
-       0x10080221,
-       0x10080320,
+       0x10080421,
+       0x10080520,
        0x10090044,
        0x100a0008,
        0x100b0000,
        0x10380400,
-       0x10080241,
-       0x100802c0,
+       0x10080441,
+       0x100804c0,
        0x100a0024,
        0x10090010,
        0x100b0000,