Merge branch 'master' of git://git.denx.de/u-boot-nios

[oweals/u-boot.git] / board / denx / m28evk / m28evk.c

diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
index 118e2222a5d64240bae11be9cfb39420b84f7c11..8cf3dc9d4e5d83f354d4f8b7b2db53d2c0ea49ed 100644 (file)
--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
@@ -52,6 +52,13 @@ int board_early_init_f(void)
        /* SSP2 clock at 96MHz */
        mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
 
+#ifdef CONFIG_CMD_USB
+       mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+       mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
+                       MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+       gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+#endif
+
        return 0;
 }
 
@@ -63,10 +70,24 @@ int board_init(void)
        return 0;
 }
 
+#define        HW_DIGCTRL_SCRATCH0     0x8001c280
+#define        HW_DIGCTRL_SCRATCH1     0x8001c290
 int dram_init(void)
 {
-       /* dram_init must store complete ramsize in gd->ram_size */
-       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+       uint32_t sz[2];
+
+       sz[0] = readl(HW_DIGCTRL_SCRATCH0);
+       sz[1] = readl(HW_DIGCTRL_SCRATCH1);
+
+       if (sz[0] != sz[1]) {
+               printf("MX28:\n"
+                       "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
+                       "HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
+                       "verify these two registers contain valid RAM size!\n");
+               hang();
+       }
+
+       gd->ram_size = sz[0];
        return 0;
 }