* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/errno.h>
#include <hwconfig.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_DRIVER_TI_EMAC
return 0;
}
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
static const struct pinmux_config gpio_pins[] = {
#ifdef CONFIG_USE_NOR
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* GP0[11] is required for SD to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
+#endif
};
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(emifa_pins_nor),
#endif
PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins),
+#endif
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
{ DAVINCI_LPSC_EMAC }, /* image download */
{ DAVINCI_LPSC_UART2 }, /* console */
{ DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
};
const int lpsc_size = ARRAY_SIZE(lpsc);
int board_init(void)
{
-#ifdef CONFIG_USE_NOR
- u32 val;
-#endif
-
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
- writel((DAVINCI_ABCR_WSETUP(0) |
- DAVINCI_ABCR_WSTROBE(1) |
- DAVINCI_ABCR_WHOLD(0) |
- DAVINCI_ABCR_RSETUP(0) |
- DAVINCI_ABCR_RSTROBE(1) |
+ writel((DAVINCI_ABCR_WSETUP(2) |
+ DAVINCI_ABCR_WSTROBE(2) |
+ DAVINCI_ABCR_WHOLD(1) |
+ DAVINCI_ABCR_RSETUP(1) |
+ DAVINCI_ABCR_RSTROBE(4) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
- clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
- val = readl(GPIO_BANK0_REG_SET_ADDR);
- val |= (0x01 << 11);
- writel(val, GPIO_BANK0_REG_CLR_ADDR);
+ writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+ /* Set the GPIO direction as output */
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+ /* Set the output as high */
+ writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC