Merge branch 'master' of git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / board / davedenx / qong / qong.c

diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 9fca1f8ddf11d952a9f9774d0d5e54884a199652..c41f11d60c75a4ed1687a5dca0334ac728262680 100644 (file)
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -28,6 +28,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <nand.h>
+#include <pmic.h>
 #include <fsl_pmic.h>
 #include <asm/gpio.h>
 #include "qong_fpga.h"
@@ -42,7 +43,7 @@ void hw_watchdog_reset(void)
 }
 #endif
 
-int dram_init (void)
+int dram_init(void)
 {
        /* dram_init must store complete ramsize in gd->ram_size */
        gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
@@ -59,7 +60,7 @@ static void qong_fpga_reset(void)
        udelay(300);
 }
 
-int board_early_init_f (void)
+int board_early_init_f(void)
 {
 #ifdef CONFIG_QONG_FPGA
        /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
@@ -119,12 +120,6 @@ int board_early_init_f (void)
        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
-       mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 
 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -142,13 +137,13 @@ int board_early_init_f (void)
        mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);       /* USBH2_DATA6 */
        mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);       /* USBH2_DATA7 */
 
-       writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+       mx31_set_gpr(MUX_PGP_UH2, 1);
 
        return 0;
 
 }
 
-int board_init (void)
+int board_init(void)
 {
        /* Chip selects */
        /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
@@ -176,11 +171,15 @@ int board_init (void)
 int board_late_init(void)
 {
        u32 val;
+       struct pmic *p;
+
+       pmic_init();
+       p = get_pmic();
 
        /* Enable RTC battery */
-       val = pmic_reg_read(REG_POWER_CTL0);
-       pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
-       pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+       pmic_reg_read(p, REG_POWER_CTL0, &val);
+       pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+       pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 
 #ifdef CONFIG_HW_WATCHDOG
        mxc_hw_watchdog_enable();
@@ -189,13 +188,13 @@ int board_late_init(void)
        return 0;
 }
 
-int checkboard (void)
+int checkboard(void)
 {
        printf("Board: DAVE/DENX Qong\n");
        return 0;
 }
 
-int misc_init_r (void)
+int misc_init_r(void)
 {
 #ifdef CONFIG_QONG_FPGA
        u32 tmp;
@@ -232,7 +231,7 @@ static void board_nand_setup(void)
 
        mxc_setup_weimcs(3, &cs3);
 
-       __REG(IOMUXC_GPR) |= 1 << 13;
+       mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
 
        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));