#include <asm/processor.h>
#include <i2c.h>
#include <miiphy.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
void sdram_init(void);
|
+-------------------------------------------------------------------------*/
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
- mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtebc (epcr, 0xa8400000); /* EBC always driven */
+ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
return 0; /* success */
}
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in cpu/ppc4xx
+ * in arch/powerpc/cpu/ppc4xx
*/
sdram_init();
tot_size = 0;
- mtdcr (memcfga, mem_mb0cf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (memcfga, mem_mb1cf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (memcfga, mem_mb2cf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
- mtdcr (memcfga, mem_mb3cf);
- tmp = mfdcr (memcfgd);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
/* AUTO neg */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
- PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
/* LEDs */
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
return 0; /* success */
}